Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 8563952
    Abstract: A charged particle beam writing apparatus, includes a unit to input information about a stripe region height, and to judge, when a write region is divided into stripe regions in a thin rectangular shape by the stripe region height, whether a height of a last stripe region is narrower than the stripe region height; and a unit to divide the write region into stripe regions in the thin rectangular shape in such a way that the last stripe region and a stripe region prior to the last stripe region are combined to create one stripe region and stripe regions at least two stripe regions prior to the last stripe region are each created as stripe regions of the stripe region height if the height of the last stripe region is narrower than the stripe region height.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 22, 2013
    Assignee: NuFlare Technology, Inc.
    Inventors: Jun Yashima, Akihito Anpo
  • Patent number: 8554510
    Abstract: Movements of a lithographic apparatus include dynamic positioning errors on one or more axes which cause corresponding errors which can be measured in the applied pattern. A test method includes operating the apparatus several times while deliberately imposing a relatively large dynamic positioning error at different specific frequencies and axes. Variations in the error in the applied pattern are measured for different frequencies and amplitudes of the injected error across a frequency band of interest for a given axis or axes. Calculation using said measurements and knowledge of the frequencies injected allows analysis of dynamic positioning error variations in frequency bands correlated with each injected error frequency.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 8, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Frank Staals, Hans Van Der Laan, Hans Butler, Gerardus Carolus Johannus Hofmans, Sven Gunnar Krister Magnusson
  • Patent number: 8555208
    Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments include obtaining qualitative data from within the pattern area of a reticle indicative of the physical characteristics of the pattern area. Additional embodiments include obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. In further embodiments qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. Several embodiments provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements. This is expected to provide accurate data for correcting the photolithography tool to compensate for variances in the pattern area, and to increase throughput because the photolithography tool is not used to measure the reticle.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Craig A. Hickman
  • Patent number: 8535858
    Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Chui Fu Chiu
  • Patent number: 8530121
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8530120
    Abstract: A method for patterning a second layer of a work piece in a direct write machine in the manufacturing of a multilayer system-in-package stack. The work piece having a first layer with a plurality of electrical components in the form of dies arbitrarily placed. Each component having connection points where some need to be connected between the components. A first pattern wherein different zones comprising connection points of dies distributed in the first layer are associated with different requirements on alignment. The method comprising the steps of: a. Detecting sacred zones in first pattern that have a high requirement on alignment to selected features of the system-in-package stack or to the placed components; b. Detecting stretch zones of the first pattern that are allowed to have a lower requirement on alignment to other features of the system-in-package stack; c.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: September 10, 2013
    Assignee: Micronic Mydata AB
    Inventors: Mikael Wahlsten, Per-Erik Gustafsson
  • Patent number: 8524426
    Abstract: A method for correcting a position error of a lithography apparatus comprises inputting position data of exposure pattern, irradiating laser light onto a position reference mask from a position measurement laser system, calculating actual position data of the laser light irradiated onto the position reference mask, and comparing the position data of the exposure pattern with the actual position data of the laser light irradiated onto the position reference mask. With this method, circuit patterns can be accurately formed at predetermined positions on a photomask, and the circuit patterns on the photomask can be accurately formed at predetermined positions on a wafer.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jin Choi, Dong-Seok Nam
  • Patent number: 8512918
    Abstract: By forming on a substrate a reference point mark having a concave or convex shape with its side walls being generally upright, even if a multilayer reflective film, an absorber film, and so on are formed over the reference point mark, sufficient contrast for inspection light is obtained so that the position of the reference point mark can be identified with high accuracy.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 20, 2013
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 8486587
    Abstract: A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Hua Tsai, Chia-Wei Huang
  • Patent number: 8486593
    Abstract: Methods of making flexible circuit films include providing a polymer film or other flexible substrate having a plurality of alignment marks and a photosensitive material thereon. The substrate passes around a suitable roller, belt, or other inelastic conveyor such that the substrate and the conveyor move together at least from a first location to a second location. Positions of a first set of the alignment marks on a first portion of the substrate are measured when such portion is at the first location, and the measured positions can be used to calculate a distortion of the substrate. The photosensitive material is then patternwise exposed when the first portion of the substrate has moved to the second location. The patternwise exposing is based on the measured positions of the first set of alignment marks, and may include exposing the web with a distortion-adjusted pattern. Related systems and articles are also disclosed.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 16, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Michael A. Haase, Jeffrey H. Tokie, Daniel J. Theis, Brian K. Nelson
  • Patent number: 8455162
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8440372
    Abstract: A single field photomask includes a first set of targets formed on a first side of the photomask, and a second set of targets formed on a second side of the photomask, opposite the first side. In operation, the photomask is to be applied to a wafer without any alignment marks. The photomask forms a first set of alignment marks in the wafer from the first set of targets, and the photomask further forms a second set of alignment marks in the wafer from the second set of targets. The first set of alignment marks is used to align to a first field mask and the second set of alignment marks is used to align to a second field mask to stitch an image of the first field mask to an image of the second field mask.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: May 14, 2013
    Assignee: Micrel, Inc.
    Inventor: Arthur Lam
  • Patent number: 8435702
    Abstract: Provided is a technique capable of improving the dimensional accuracy of a transfer pattern in a lithography technique in which EUV light is used and the EUV light is incident obliquely on a mask and an image of the EUV light reflected from the mask is formed on a semiconductor substrate (resist film), thereby transferring the pattern formed on the mask onto the semiconductor substrate. The present invention is based on a lithography technique in which EUV light is used and an exposure optical system in which the EUV light is obliquely incident on a mask is used. In this lithography technique, an absorber and a difference in level are formed on the mask, and a projective component projected on a mask surface out of a direction cosine component of the incident light is set to be almost orthogonal to an extending direction of the difference in level.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: May 7, 2013
    Assignees: Renesas Electronics Corporation, Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Terasawa, Takeshi Yamane
  • Patent number: 8432548
    Abstract: Systems and methods for alignment of template and substrate at the edge of substrate are described.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: April 30, 2013
    Assignee: Molecular Imprints, Inc.
    Inventors: Byung-Jin Choi, Pawan Kumar Nimmakayala, Philip D. Schumaker
  • Patent number: 8431827
    Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroshi Nishikawa, Taro Hirai
  • Patent number: 8411271
    Abstract: A plurality of wafer marks on a wafer is detected while a wafer stage moves from a loading position where a wafer is delivered onto the wafer stage to an exposure starting position where exposure of a wafer begins, with a part of an alignment system also moving, using the alignment system. Accordingly, the time required for mark detection can be reduced, therefore, it becomes possible to increase the throughput of the entire exposure process.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 2, 2013
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8404410
    Abstract: An exposure system includes an exposure device and an image processing device. The exposure device includes a plurality of cameras. Each of the cameras is configured so as to be selectively set to a full scan mode and a partial scan mode. The camera transmits all of obtained image data in the full scan mode, and extracts part of the obtained image data and transmits the partial image data in the partial scan mode. The image processing device paratactically performs processing using the image data transmitted from the camera and processing using the image data transmitted from the camera.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 26, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kousuke Murakami, Akira Arima, Tomohiro Hattori, Shuuhei Miyazaki
  • Patent number: 8399160
    Abstract: Provided is a reflective mask blank, wherein even if inspection light for defect inspection is irradiated onto an uppermost surface of a multilayer reflective film or of an absorber film formed over a reference point mark, sufficient contrast is obtained between a position of the reference point mark and its peripheral portion so that the position of the reference point mark can be identified with high accuracy. By forming a reference point mark (11) in the form of a recess having a depth of 10 ?m or more and a width of 80 ?m or more on a main surface of a substrate (12), even if a multilayer reflective film (13), an absorber film (15), and so on are formed over the reference point mark (11), sufficient contrast for the inspection light is obtained so that the position of the reference point mark (11) can be identified with high accuracy.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: March 19, 2013
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 8399163
    Abstract: When an alignment mark does not exist within an area of an image obtained by a camera, the coordinate of the alignment mark is calculated based on an identification mark existing in the area of the image and a previously stored positional relationship between the alignment mark and the identification mark. A distance by which a long-sized base material is to be moved for causing the alignment mark to be positioned within the imaging area of the camera is calculated based on the calculated coordinate of the alignment mark, and the long-sized base material is moved by the calculated distance.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kousuke Murakami, Akira Arima, Tomohiro Hattori, Shuuhei Miyazaki
  • Patent number: 8384900
    Abstract: An exposure apparatus includes a controller configured to calculate a position of an alignment mark detected by a detector, to approximate a deformation of a substrate by using an approximation equation, to calculate a correction amount of each of the plurality of shots, and to control driving of a stage in exposing each shot based on a correction amount that is calculated. The approximation equation is defined as a sum of a first term representative of a deformation of the entire substrate, and at least one of a second term representative of a distortion of a shot arrangement and a third term representative of a shot shape.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: February 26, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 8383324
    Abstract: A method of manufacturing a semiconductor device comprising forming an active region in a device substrate using a first phase shift mask (PSM) having a first patterned light shielding layer formed thereon, forming a polysilicon feature on the device substrate over the active region using a second PSM having a second patterned light shielding layer formed thereon, forming a contact feature on the polysilicon feature using a third PSM having a third patterned light shielding layer formed thereon, and forming a metal feature on the contact feature using a fourth PSM having a fourth patterned light shielding layer formed thereon, wherein at least one of the third and fourth patterned light shielding layers is patterned substantially similarly to at least one of the first and second patterned light shielding layers.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Ming Lin
  • Patent number: 8367284
    Abstract: An exposure device includes a determining unit determines specific transfer patterns, which are transfer patterns of predetermined portions of a unit pattern, among transfer patterns projected through a photomask including an internal pattern having a plurality of unit patterns that is arranged at a predetermined interval and has the same shape, for two or more unit patterns, an error calculating unit calculates an error between the transfer pattern and the specified transfer pattern on the basis of the comparison between the relative position between the specific transfer patterns and a specified value of it, a correction parameter calculating unit calculates correction parameters for correcting the transfer patterns on the basis of the calculated error, and a correction control unit corrects exposure conditions using the correction parameters such that the transfer patterns are corrected.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kyoichi Tsubata
  • Patent number: 8361684
    Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Hsin-Yi Tsai, Min Cao
  • Patent number: 8361683
    Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Allen H. Gabor, Nelson M. Felix
  • Patent number: 8361679
    Abstract: A phase shift mask having a first region and a second region in a transverse direction includes a transparent layer, a phase shift pattern disposed in the first region, a transmittance control layer pattern disposed in the second region, and a shading layer pattern disposed on the transmittance control layer pattern. The phase shift pattern has a first pattern including a transparent material and a second pattern including metal. The phase shift mask may prevent haze effects through a cleaning process using an alkaline cleaning solution.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Se-Gun Moon, Dong-Seok Nam, Hoon Kim
  • Patent number: 8354209
    Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 15, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Bob Streefkerk, Johannes Jacobus Matheus Baselmans, Sjoerd Nicolaas Lambertus Donders, Jeroen Johannes Sophia Maria Mertens, Johannes Catharinus Hubertus Mulkens, Christiaan Alexander Hoogendam
  • Patent number: 8345244
    Abstract: An exposure apparatus includes a controller configured to calculate a position of an alignment mark detected by a detector, to approximate a deformation of a substrate by using an approximation equation, to calculate a correction amount of each of the plurality of shots, and to control driving of a stage in exposing each shot based on a correction amount that is calculated. The approximation equation is defined as a sum of a first term representative of a deformation of the entire substrate, and at least one of a second term representative of a distortion of a shot arrangement and a third term representative of a shot shape.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: January 1, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 8343693
    Abstract: A focus test reticle for measuring focus information includes an outer pattern. The outer pattern has a line pattern composed of a light shielding film extending in the Y direction, a phase shift portion provided on a side in the +X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the ?X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the +X direction of the phase shift portion, and a phase shift portion provided on a side in the ?X direction of the transmitting portion. Focus information of a projection optical system is measured at a high measuring reproducibility and a high measuring efficiency.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Nikon Corporation
    Inventors: Shigeru Hirukawa, Shinjiro Kondo
  • Patent number: 8329360
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8329366
    Abstract: A method is described for alignment of a substrate during a double patterning process. A first resist layer containing at least one alignment mark is formed on the substrate. After the first resist layer is developed, a second resist layer is deposited over the first resist layer, leaving a planar top surface (i.e., without topography). By baking the second resist layer appropriately, a symmetric alignment mark is formed in the second resist layer with little or no offset error from the alignment mark in the first resist layer. The symmetry of the alignment mark formed in the second resist can be enhanced by appropriate adjustments of the respective thicknesses of the first and second resist layers, the coating process parameters, and the baking process parameters.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: December 11, 2012
    Assignees: ASML Netherlands B.V., ASML Holding N.V.
    Inventors: Maya Angelova Doytcheva, Mircea Dusa, Richard Johannes Franciscus Van Haren, Harry Sewell, Robertus Wilhelmus Van Der Heijden
  • Patent number: 8323860
    Abstract: A solid-state imaging device producing method includes the steps of: applying a resist material onto a substrate in which a channel region is formed; forming a resist layer by exposure and development of the resist material using a mask, the resist layer having an opening and a thin-film portion, the mask having a first region through which light is transmitted and a second region through which a smaller quantity of light than that the light transmitted through the first region is transmitted; subjecting the substrate to ion implantation using the resist layer as a mask to form an impurity region; etching the substrate using the resist layer as a mask after the ion implantation to form an alignment mark; and forming an electrode on the impurity region and part of the channel region using the alignment mark as a reference.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shu Sasaki
  • Patent number: 8318392
    Abstract: An alignment method is disclosed, in which a distance between a substrate and a photomask is set at a predetermined exposure gap. The photomask is rectangular, and includes a first side, and a second side opposite to the first side. A distance between a midpoint of the first side and the substrate is matched with the exposure gap. The photomask is rotated about, as an axis, a line that connects the midpoint of the first side and a midpoint of the second side to each other, whereby distances between both ends of the first side and the substrate are individually matched with the exposure gap. The photomask is rotated about the first side taken as an axis, whereby a distance between the midpoint of the second side and the substrate is matched with the exposure gap.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: November 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryota Hamada, Tomohiro Murakoso
  • Patent number: 8313877
    Abstract: A photolithography monitoring mark on a substrate includes a plurality of sets of lines. Individual of the sets include a plurality of substantially parallel lines comprising different widths arrayed laterally outward in opposing lateral directions from an axial center of the set. The different widths decrease in each of the opposing lateral directions laterally outward from the axial center of the set. Other implementations are disclosed.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Woong Jae Chung
  • Patent number: 8309282
    Abstract: An apparatus and method for aligning a mask that includes disposing and firstly aligning a mask over a first substrate, with a space interposed therebetween, bringing the mask into contact with the first substrate and then measuring the alignment state of the mask with respect to the first substrate to detect an alignment error, secondly aligning the mask with respect to the first substrate based on the alignment error, transferring the first substrate to the next process, disposing and thirdly aligning the mask over a second substrate with the space interposed therebetween, and bringing the mask into contact with the second substrate.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 13, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung-Hoon Chung, Hyung-Min Kim
  • Patent number: 8304173
    Abstract: The method of forming a pattern includes forming a first photosensitive layer pattern including a first pattern in a first region of a substrate and a second pattern in a second region of the substrate, by performing a first photolithography process using a photomask having a first mask region and a second mask region. The first pattern is transferred from the first mask region, and the second pattern is transferred from the second mask region. The method further includes forming a second photosensitive layer pattern including a third pattern in the second region of the substrate and a fourth pattern in the first region of the substrate, by performing a second photolithography process using the photomask. The third pattern is transferred from the first mask region, and the fourth pattern is transferred from the second mask region.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Yu, Sung-Hyuck Kim, Gi-Sung Yoon
  • Patent number: 8288063
    Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Rung Lu, Chih Ming Hong, Yen-Di Tsen
  • Patent number: 8289516
    Abstract: A method of measuring focus of a lithographic projection apparatus includes exposure of a photoresist covered test substrate with a plurality of verification fields. Each of the verification fields includes a plurality of verification markers, and the verification fields are exposed using a predetermined focus offset FO. After developing, an alignment offset for each of the verification markers is measured and translated into defocus data using a transposed focal curve. The method according to an embodiment of the invention may result in a focus-versus alignment shift sensitivity up to 50 times higher (typically dX,Y/dZ=20) than conventional approaches.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: October 16, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Gerardus Carolus Johannus Hofmans, Hubertus Antonius Geraets, Mark Zellenrath, Sven Gunnar Krister Magnusson
  • Patent number: 8278014
    Abstract: A photomask includes a transparent substrate having a transparent property against exposing light, a semi-light-shielding portion formed on the transparent substrate, a first opening formed in the semi-light-shielding portion and having a first dimension and a second opening formed in the semi-light-shielding portion and having a second dimension lager than the first dimension. A phase-shifting portion which transmits the exposing light in an opposite phase with respect to the first opening is formed on the transparent substrate around the first opening. A light-shielding portion is formed on the transparent substrate around the second opening.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 2, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigeo Irie, Akio Misaka, Yuji Nonami, Tetsuya Nakamura, Chika Harada
  • Publication number: 20120244459
    Abstract: A mask for evaluating overlay error comprises a plurality of replicate device regions and an overlay mark. The plurality of replicate device regions are disposed uniformly on the mask, wherein each comprises a plurality of device patterns; and a plurality of current layer check patterns are formed adjacent to the plurality of device patterns. The overlay mark is formed on the corner of the mask's peripheral region. In particular, the current layer check patterns are configured to evaluate the pattern offset of a current mask, and the overlay mark and the current layer check patterns are configured to evaluate the overlay error by performing an exposure process using the current mask and a next mask.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Kuan Ting CHOU, Pei Cheng FAN
  • Patent number: 8260033
    Abstract: A method is provided for determining the relative overlay shift of stacked layers, said method comprising the steps of: a) providing a reference image including a reference pattern that comprises first and second pattern elements; b) providing a measurement image of a measurement pattern, which comprises a first pattern element formed by a first one of the layers and a second pattern element formed by a second one of the layers; c) weighting the reference or measurement image such that a weighted first image is generated, in which the first pattern element is emphasized relative to the second pattern element; d) determining the relative shift of the first pattern element on the basis of the weighted first image and of the measurement or reference image not weighted in step c); e) weighting the reference or measurement image such that a weighted second image is generated, in which the second pattern element is emphasized relative to the first pattern element; f) determining the relative shift of the second pat
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: September 4, 2012
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Michael Arnz, Gerd Klose
  • Patent number: 8252489
    Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
  • Patent number: 8252491
    Abstract: A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has a larger pitch than the pattern. Finally, one of the two feature types is selectively etched in the open areas. The result is a marker with a large pitch suitable to be read with long wavelength radiation but the edges of the features are defined in an exposure step having a pitch comparable to the product features.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 28, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Maurits Van Der Schaar
  • Patent number: 8243273
    Abstract: A semiconductor wafer may include a dummy field configured to enable overlay measurements. The enhanced dummy field may include a plurality of encoding blocs that enable OVL measurements to be made throughout the enhanced dummy field.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 14, 2012
    Assignee: KLA-Tencor Corporation
    Inventors: Vladimir Levinski, Michael Adel, Mark Ghinovker, Alexander Svizher
  • Patent number: 8236464
    Abstract: A method for making a mask, in which, an imprinting lithography process is employed to form a pattern in a first region of a mask substrate, and an E-beam writing process is employed to form another pattern in a second region of the mask substrate. Furthermore, these two patterns may be well stitched through an optical alignment process in an E-beam writing chamber.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: August 7, 2012
    Assignee: Inotera Memories, Inc.
    Inventor: Tah-Te Shih
  • Patent number: 8216382
    Abstract: A foreign matter removal method that removes foreign matter attached to a surface of a substrate having been subjected to predetermined processing. An edge of a rotating substrate mounted on a mounting stage is irradiated with misalignment measurement laser light. The misalignment measurement laser light other than the laser light blocked by the edge of the substrate is received, and power thereof is detected. The amount of misalignment of the substrate is calculated based on the detected power of the misalignment measurement laser light and a detected rotation angle of the rotating substrate. The misalignment of the substrate is corrected for based on the calculated amount of misalignment. After that, foreign matter removal laser light is irradiated, and a process gas that is to react with the foreign matter is jetted to the edge of the substrate. Consequently, the foreign matter attached to the substrate is decomposed and removed.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Takehiro Shindo
  • Patent number: 8203223
    Abstract: A target and method for use in polarized light lithography. A preferred embodiment comprises a first structure located on a reference layer, wherein the first structure is visible through a second layer, and a second structure located on the second layer, wherein the second structure is formed from a photomask containing a plurality of sub-structures oriented in a first orientation, wherein a polarized light is used to pattern the second structure onto the second layer, and wherein a polarization of the polarized light is the same as the orientation of the plurality of sub-structures. The position, size, and shape of the second structure is dependent upon a polarity of the polarized light, permitting a single design for an overlay target to be used with different polarities of polarized light.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 19, 2012
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Patent number: 8187773
    Abstract: A method for generating data on mask pattern used to form a device pattern formed on a reflective exposure mask, wherein data on the mask pattern is generated based on a position correction amount table used to correct an amount of transfer position error occurring depending on at least one of pattern size and pattern pitch of the mask pattern when the mask pattern is transferred onto an exposure target member.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Nakajima, Masaru Suzuki, Takashi Sato
  • Patent number: 8187778
    Abstract: A method for correcting a position error of a lithography apparatus comprises inputting position data of exposure pattern, irradiating laser light onto a position reference mask from a position measurement laser system, calculating actual position data of the laser light irradiated onto the position reference mask, and comparing the position data of the exposure pattern with the actual position data of the laser light irradiated onto the position reference mask. With this method, circuit patterns can be accurately formed at predetermined positions on a photomask, and the circuit patterns on the photomask can be accurately formed at predetermined positions on a wafer.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Dong-Seok Nam
  • Patent number: 8183123
    Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: May 22, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 8137875
    Abstract: Methods and apparatuses for patterning workpieces are provided. The methods and apparatuses described herein improve overlay between subsequently patterned layers on a workpiece by introducing an improved alignment method that compensates for workpiece distortions.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 20, 2012
    Assignee: Micronic-Mydata AB
    Inventors: Fredrik Sjöström, Mikael Wahlsten