Material Deposition Only Patents (Class 430/315)
  • Patent number: 11923198
    Abstract: In a first aspect, the present disclosure relates to a method for forming a patterning mask over a layer to be patterned, the method comprising: (a) providing a first layer over a substrate, the substrate comprising the layer to be patterned, the first layer being capable to bond with a monolayer comprising a compound comprising a functional group for bonding to the first layer and a removable organic group, (b) bonding the monolayer to the first layer, (c) exposing the monolayer to an energy beam, thereby forming a pattern comprising a first area comprising the compound with the removable organic group and a second area comprising the compound not having the removable organic group, and (d) selectively depositing an amorphous carbon layer on top of the first area.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: March 5, 2024
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Mikhail Krishtab, Silvia Armini
  • Patent number: 11862928
    Abstract: A laser source includes a semiconductor pad containing an active waveguide arranged on a functionalized substrate having an integrated waveguide. The integrated waveguide is formed from a stack of a first portion and of a second portion. A Bragg grating is arranged in the first portion and is covered by the second portion.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 2, 2024
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Karim Hassan, Laetitia Adelmini, Bertrand Szelag
  • Patent number: 11832504
    Abstract: A method for fabricating an organic electronic device comprises providing a plurality of photoresist structures on a substrate, the substrate having a first electrode layer, the photoresist structures having a bottom surface attached to the substrate and a top surface opposite the bottom surface, the top surface having a dimension greater than a dimension of the bottom surface, positioning a mask over the structures, the mask having a plurality of openings, and depositing an emissive material over the substrate through at least one of the plurality of openings to form at least one emissive element. An organic electronic device and a method of fabricating an organic electronic component are also described.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 28, 2023
    Assignee: The Regents of the University of Michigan
    Inventor: Stephen R. Forrest
  • Patent number: 11798723
    Abstract: A multilayer metal film disposed on a base having insulating properties includes a first metal film that is in contact with the base and that is electrically conductive, a second metal film covering the first metal film from a side of the first metal film opposite to the base, the second metal film having resistance to solder leaching, and a catalytic layer disposed between the first metal film and the second metal film, the catalytic layer having a protruding portion protruding toward the second metal film, the protruding portion extending into the second metal film.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 24, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Namiko Sasajima, Hiroki Imaeda, Masami Okado, Shinji Otani, Tomohiro Sunaga, Yoshimasa Yoshioka
  • Patent number: 11796568
    Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: October 24, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 11774818
    Abstract: A display substrate including: a base substrate, wherein at least one bonding element to be electrically connected to an external component is disposed in a peripheral region of the base substrate. The bonding element includes a first conductive layer, a second conductive layer and an insulation layer. The first conductive layer includes a metal oxide conductive lead. The second conductive layer includes a metal conductive lead. One or more via holes are provided in a region of the insulation layer. The metal conductive lead is electrically connected to the metal oxide conductive lead through the one or more via holes. The bonding element further comprises a via hole protection layer. A reflective liquid crystal display panel and an electrical apparatus are provided.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: October 3, 2023
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhaofan Liu, Xianxue Duan, Zhihai Zhang
  • Patent number: 11678441
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: June 13, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 11609492
    Abstract: A device having a color photo resist pattern includes a 3D substrate, at least one color photo resist layer and at least one circuit pattern layer. The at least one color photo resist layer is formed on said 3D substrate and forms a visual pattern together. The at least one circuit pattern layer is formed on said visual pattern formed by said at least one color photo resist layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 21, 2023
    Inventor: Ming-An Hsu
  • Patent number: 11569190
    Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 11526054
    Abstract: A display device includes: a first substrate, including: a gate line having an extension direction; a switch unit electrically connecting to the gate line; a pixel electrode electrically connecting to the switch unit; and a slit in the pixel electrode, wherein a virtual line parallel to the extension direction passes through an end point of the slit which is closest to the gate line, and the pixel electrode is divided into a first portion and a second portion by the virtual line, wherein the first portion is closer to the gate line than the second portion, the first portion and the second portion respectively have a first width and a second width along the extension direction, the first width is a maximum width of the first portion, the second width is a maximum width of the second portion, and the second width is less than the first width.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: December 13, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Shun-Chen Yang, Ying-Tong Lin
  • Patent number: 11449040
    Abstract: A cleaning device for a display panel is configured with a sensor corresponding to a water jet nozzle, and a control switch which suspends an operation of the device when the water jet nozzle is detected as working abnormally, thereby preventing abnormal products from being produced due to the failure of finding an abnormal condition of the water jet nozzle in time, ensuring the normal process of the product, and preventing the nonessential economic loss.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 20, 2022
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Chung-Kuang Chien
  • Patent number: 11415600
    Abstract: A probe card for testing a device under test having a plurality of contact pads includes a support plate having first contact pads thereon. A flexible membrane has a first face and a peripheral portion including second contact pads thereon. A plurality of contact probes are associated with a first face of the flexible membrane and are configured to abut onto the plurality of contact pads of the device under test. A sliding contact area includes: the first contact pads formed on the support plate; the second contact pads formed on the peripheral portion of the flexible membrane, the peripheral portion of the flexible membrane configured to come in pressing contact onto the support plate at the sliding contact area. A pressing element contacts the peripheral portion of the flexible membrane at the sliding contact area, and the pressing element puts the second contact pads into pressing contact with the first contact pads.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: August 16, 2022
    Assignee: Technoprobe S.p.A.
    Inventor: Riccardo Vettori
  • Patent number: 11409198
    Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a polymer including a structural unit represented by Chemical Formula 1, wherein, in Chemical Formula 1, A is a substituted or unsubstituted dihydroxypyrene moiety, and E is a substituted or unsubstituted pyrenyl group.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Seunghyun Kim, Yushin Park, Hyungseok Park, Sunghwan Kim, Hyeonil Jung
  • Patent number: 11380552
    Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.
    Type: Grant
    Filed: April 25, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunchul Yoon, Mincheol Kwak, Joonghee Kim, Jihee Kim, Yeongshin Park, Jungheun Hwang
  • Patent number: 11305509
    Abstract: A method of manufacturing a sandwich structure having an open cellular core and a fluid-tight seal surrounding the core includes coupling a mold to a first facesheet to define a reservoir. The method also includes irradiating a volume of photo-monomer in the reservoir with a series of vertical collimated light beams to form a cured, solid polymer border extending around a periphery of the first facesheet. The method also includes irradiating a remaining volume of photo-monomer in the reservoir with a series of collimated light beams to form an ordered three-dimensional polymer microstructure core defined by a plurality of interconnected polymer optical waveguides coupled to the first facesheet and surrounded by the cured, solid polymer border. The method further includes coupling a second facesheet to the ordered three-dimensional microstructure core and the cured, solid polymer border to form the sandwich structure.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 19, 2022
    Assignee: HRL Laboratories, LLC
    Inventors: Jacob M. Hundley, Alan J. Jacobsen, Sophia S. Yang, Zak C. Eckel, Christopher S. Roper, William Carter
  • Patent number: 11259415
    Abstract: In conventional fluid discharge devices, a discharge head used should be increased in size according to increase in size of a workpiece such as silicon wafer. However, if the discharge head increases in length, a deformation amount of a mask used for discharging the fluid on the workpiece increases, thereby the discharging amount varies. Discharging the fluid in a reciprocating manner is performed using a fluid discharging device including a head unit having a width shorter than a length of the workpiece. A suction port having opening portions each having a slit shape are disposed on the both sides of the discharge nozzle in a vicinity of the discharge nozzle.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 22, 2022
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Hideki Nakamura, Takashi Nauchi, Toshihiko Mutsuji, Ryoichi Suzuki
  • Patent number: 11175582
    Abstract: This disclosure relates to a photosensitive stacked structure that includes first and second layers, in which the first layer is a photosensitive, dielectric layer and the second layer is a photosensitive layer. The dissolution rate of the first layer in a developer is less than the dissolution rate of the second layer in the developer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 16, 2021
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Sanjay Malik, Raj Sakamuri, Ognian N. Dimov, Binod B. De, William A. Reinerth, Ahmad A. Naiini
  • Patent number: 11155093
    Abstract: A method of producing a structure having a through substrate includes: forming a protective member having an atmosphere communication layer having a structure communicating with the through hole by permeation from at least a part of a layer side surface part to the through hole, and a gas-impermeable protective layer in this order, on the second surface of the through substrate; forming a dry film resist layer having a resin layer and a support member in this order, on the first surface of the through substrate; and peeling the support member from the resin layer, the support member being peeled from the resin layer in a state that the through hole of the through substrate is communicated with atmosphere by at least the atmosphere communication layer, in the peeling.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 26, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Manabu Otsuka, Tamaki Sato, Tetsushi Ishikawa, Yasuaki Tominaga
  • Patent number: 10910376
    Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Mo Park, Ju Youn Kim, Hyung Joo Na, Sang Min Yoo, Eui Chul Hwang
  • Patent number: 10910010
    Abstract: A reversible recording medium according to an embodiment of the present disclosure is a reversible recording medium that includes recording layers and heat-insulating layers that are alternately stacked, in which the recording layers each include a reversible heat-sensitive color developing composition and a first light-heat converting agent. In this reversible recording medium, the recording layers are different from each other in a developing color of their respective reversible heat-sensitive color developing compositions and are different from each other in an absorption wavelength of their respective first light-heat converting agents. This reversible recording medium further includes a heat-generating layer that includes a second light-heat converting agent having an absorption wavelength that is different from the absorption wavelength of the first light-heat converting agent included in each of the recording layers.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 2, 2021
    Assignee: Sony Corporation
    Inventors: Isao Takahashi, Satoko Asaoka, Taichi Takeuchi, Asuka Tejima, Kentaro Kuriyama, Mitsunari Hoshi
  • Patent number: 10877374
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method can include a film formation process, and a exposure process. The film formation process forms a pattern formation material film on a base body. The pattern formation material film includes a pattern formation material including a first portion and a second portion. The first portion includes at least one of acrylate or methacrylate. The second portion includes an alicyclic compound and a carbonyl group. The alicyclic compound has an ester bond to the at least one of the acrylate or the methacrylate. The carbonyl group is bonded to the alicyclic compound. The exposure process causes the pattern formation material film to expose to a metal compound including a metallic element.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Koji Asakawa, Seekei Lee, Naoko Kihara, Norikatsu Sasao, Tomoaki Sawabe, Shinobu Sugimura
  • Patent number: 10790459
    Abstract: A stretchable film includes a first region including a plurality of first patterns having a concave polygonal shape. The stretchable film also includes a second region including a plurality of second patterns having a concave polygonal shape. The stretchable film further includes a buffer region between the first region and the second region.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Jin Joo, Won-Il Choi, Jong-Ho Hong
  • Patent number: 10676392
    Abstract: Described are carbon nanotube dispersions containing single-walled carbon nanotubes dispersed in a dispersant solution comprising a solvent (water, organic polar protic solvents, and/or organic polar aprotic solvents), and an azo compound. The single-walled carbon nanotubes are not cross-linked with covalent bonds. The dispersions are useful for fabricating transparent conductive thin films on flexible and inflexible substrates. Methods for making the transparent conductive thin films are also described.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 9, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Sundaram Gunasekaran, Ashok Kumar Sundramoorthy
  • Patent number: 10643840
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. A layer is selectively formed on the second surface and defects of the layer are formed on the blocking layer. The defects are removed from the blocking layer on the first surface.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey W. Anthis, Chang Ke, Pratham Jain, Benjamin Schmiege, Guoqiang Jian, Michael S. Jackson, Lei Zhou, Paul F. Ma, Liqi Wu
  • Patent number: 10515801
    Abstract: Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 10507321
    Abstract: In some examples, a medical device system a thin film including at least one electrically conductive track extending between at least one electrode and at least one electrical contact, a first and second polymer layer; wherein, at a portion of the thin film between the at least one electrode and the at least one electrical contact, the first polymer layer and second polymer layer surround the at least one electrically conductive track; and at least one discrete ceramic member located between the first and second polymer layers at a portion of the thin film between the at least one electrode and the at least one electrical contact, wherein the at least one discrete ceramic member does not surround the at least one conductive track, and wherein the at least one discrete ceramic member is configured to increase adhesion between the first polymer layer and second polymer layer.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 17, 2019
    Assignee: Medtronic Bakken Research Center B.V.
    Inventors: Edward Willem Albert Young, Gijs Peters, Erik van Veenendaal
  • Patent number: 10490778
    Abstract: A light emitting device includes a window over a light emitting pixel. A light reflection performance of the light emitting pixel to an incoming ambient light is configured by the window to be appeared to have at least two regions, wherein one region of the at least two regions has a smaller transmittance to the incoming ambient light than the other.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: November 26, 2019
    Assignee: INT TECH CO., LTD.
    Inventors: Li-Min Huang, Li-Chen Wei
  • Patent number: 10471700
    Abstract: A three-dimensional object manufacturing apparatus that may be equipped to efficiently separate a three-dimensional object from a mounting unit is provided. The printing apparatus includes: a mounting unit having a mounting surface on which a three-dimensional object being manufactured is mounted; a separator to separate the three-dimensional object from the mounting unit; a moving unit to move the three-dimensional object remaining on the mounting surface and the separator unit relative to each other after the manufacturing of the three-dimensional object is completed, the three-dimensional object on the mounting surface and the separator being moved to arrive at a separating position at which the three-dimensional object is separated by the separator; and a controller that controls the moving unit.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 12, 2019
    Assignee: MIMAKI ENGINEERING CO., LTD.
    Inventor: Kunio Hakkaku
  • Patent number: 10257926
    Abstract: A method of producing a wired circuit board including an insulating layer and a conductive pattern, including: (1), an insulating layer having an inclination face, (2), a metal thin film provided at least on the inclination face, (3), a photoresist provided on the surface of the metal thin film, (4), a light shield portion of a photomask disposed so that a first portion, where the conductive pattern is to be provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask, (5), the first portion of the photoresist is removed to expose the metal thin film corresponding to the first portion, and (6), the conductive pattern is provided on the surface of the metal thin film exposed from the photoresist.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 9, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Yoshito Fujimura, Hiroyuki Tanabe
  • Patent number: 10133179
    Abstract: A pattern treatment method, comprising: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition to the patterned feature, wherein the pattern treatment composition comprises: a block copolymer and an organic solvent, wherein the block copolymer comprises: (i) a first block comprising a first unit formed from 4-vinyl-pyridine, and (ii) a second block comprising a first unit formed from a vinyl aromatic monomer; and (c) removing residual pattern shrink composition from the substrate, leaving a coating of the block copolymer over the surface of the patterned feature, thereby providing a reduced pattern spacing as compared with a pattern spacing of the patterned feature prior to coating the pattern treatment composition. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 20, 2018
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Jin Wuk Sung, Mingqi Li, Jong Keun Park, Joshua A. Kaitz, Vipul Jain, Chunyi Wu, Phillip D. Hustad
  • Patent number: 9881793
    Abstract: A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Mahmoud Khojasteh, Deborah A. Neumayer, John Papalia, Hsinyu Tsai
  • Patent number: 9809672
    Abstract: Polymeric reaction products of certain aromatic alcohols with certain aromatic aldehydes are useful as underlayers in semiconductor manufacturing processes.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 7, 2017
    Assignees: Rohm and Haas Electronic Materials LLC, Rohm and Haas Electronic Materials Korea Ltd
    Inventors: Li Cui, Sung Wook Cho, Mingqi Li, Shintaro Yamada, Peter Trefonas, III, Robert L. Auger
  • Patent number: 9726788
    Abstract: A method for fabricating a nanoantenna array may include forming a resist layer on a substrate, forming a focusing layer having a dielectric microstructure array on the resist layer, diffusing light one-dimensionally in a specific direction by using a linear diffuser, forming an anisotropic pattern on the resist layer by illuminating the light diffused by the linear diffuser on the focusing layer and the resist layer, depositing a material suitable for a plasmonic resonance onto the substrate and the resist layer on which the pattern is formed, and forming a nanoantenna array on the substrate by removing the resist layer and the material deposited on the resist layer. A light diffusing angle by the linear diffuser and a size of the dielectric microstructure are determined based on an aspect ratio of the pattern to be formed.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 8, 2017
    Assignee: Korea Institute of Science and Technology
    Inventors: Kyeong Seok Lee, Won Mok Kim, Taek Sung Lee, Wook Seong Lee, Doo Seok Jeong, Inho Kim
  • Patent number: 9529126
    Abstract: A Fresnel zone plate is provided for encountering incident light having a wavelength. The Fresnel zone plate has a focal length and a wafer including alternating transparent and opaque zones, and a mourning surface. A plurality of silicon nanowires extend into opaque zone of the wafer. A mechanically stretchable tuning structure is mounted to the mounting surface such that stretching of the tuning structure varies the focal length of the Fresnel zone plate.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: December 27, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Hongrui Jiang, Yen-Sheng Lu, Hewei Liu
  • Patent number: 9530976
    Abstract: A method of making a structure having a patterned a base layer and useful in the fabrication of optical and electronic devices including bioelectronic devices includes, in one embodiment, the steps of: a) providing a layer of a radiation-sensitive resin; b) exposing the layer of radiation-sensitive resin to patterned radiation to form a base layer precursor having a first pattern of exposed radiation-sensitive resin and a second pattern of unexposed radiation-sensitive resin; c) providing a layer of fluoropolymer in a third pattern over the base layer precursor to form a first intermediate structure; d) treating the first intermediate structure to form a second intermediate structure; and e) selectively removing either the first or second pattern of resin by contacting the second intermediate structure with a resin developing agent, thereby forming the patterned base layer.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 27, 2016
    Assignee: ORTHOGONAL, INC.
    Inventors: Marc Ferro, George Malliaras
  • Patent number: 9466368
    Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 11, 2016
    Assignee: DEEP SCIENCE, LLC
    Inventors: Roderick A. Hyde, Muriel Y. Ishikawa, Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer, Lowell L. Wood, Jr.
  • Patent number: 9466529
    Abstract: The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity (4), which is filled with a gas, and forming at least one opening (5) in the mask at a distance from the recess or trench, the distance (6) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 11, 2016
    Assignee: AMS AG
    Inventors: Guenther Koppitsch, Ewald Stueckler, Karl Rohracher, Jordi Teva
  • Patent number: 9412734
    Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTORINCS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
  • Patent number: 9391021
    Abstract: A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: July 12, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventor: Mou-Shiung Lin
  • Patent number: 9354408
    Abstract: A structure is formed which is prepared as a via for electrical contact passing through layers of an optical waveguide, in a multilayer structure including an electrical substrate and the laminated layers of the optical waveguide. The surface of an electrode pad is plated with solder. The layers of the optical waveguide are formed above the portion plated with solder are removed to expose the portion plated with solder. A device is prepared having both a light-emitter or photoreceptor in optical contact with the optical waveguide, and a stud (pillar). The stud (pillar) is inserted into the portion in which layers of the optical waveguide have been removed, and the plated solder is melted to bond the electrode pad on top of the electrical substrate to the tip of the inserted stud (pillar).
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hirokazu Noma, Keishi Okamoto, Masao Tokunari, Kazushige Toriyama, Yutaka Tsukada
  • Patent number: 9324962
    Abstract: According to an aspect of the present invention, an organic luminescence display includes a substrate, a first electrode on the substrate, a pixel defining layer on the first electrode and partially exposing the first electrode, an auxiliary layer on the pixel defining layer, an organic layer on the first electrode and an edge of the auxiliary layer, and a second electrode on the organic layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: April 26, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jun-Young Kim
  • Patent number: 9285681
    Abstract: The invention relates to a photosensitive resin composition, and an overcoat and/or spacer for a liquid crystal display component. The photosensitive resin composition comprises an alkali-soluble resin (A), a compound having an ethylenically unsaturated group (B); a photoinitiator (C); a solvent (D); and an organic acid (E). The alkali-soluble resin (A) comprises a resin having an unsaturated group (A-1) synthesized by polymerizing a mixture, and the mixture comprises an epoxy compound having at least two epoxy groups (i) and a compound having at least one carboxyl group and at least one vinyl unsaturated group (ii). A molecular weight of said organic acid (E) is below 1000.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 15, 2016
    Assignee: CHI MEI CORPORATION
    Inventor: Li-Ting Hsieh
  • Patent number: 9159677
    Abstract: A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Xinyu Zhang, Soichi Sugiura, Yu Zeng
  • Patent number: 9153352
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa
  • Patent number: 9115297
    Abstract: An adhesive composition of this invention includes a hydrocarbon resin and a solvent for dissolving the hydrocarbon resin, the solvent containing a condensed polycyclic hydrocarbon. Thus, an adhesive composition having excellent product stability is provided.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 25, 2015
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Hirofumi Imai, Koki Tamura, Atsushi Kubo, Takahiro Yoshioka
  • Patent number: 9093448
    Abstract: In a first aspect of the present invention, a method for manufacturing a flip chip package is provided comprising the steps of a) providing a chip having electrically conductive pads on an active surface thereof, b) coating at least a portion the chip with a protectant composition comprising a polymerizable component comprising a thermosetting epoxy resin, at least 50 weight percent of a substantially transparent filler having a coefficient of thermal expansion of less than 10 ppm/° C., a photoinitator, and a solvent carrier, wherein the protectant composition comprises a thixotropic index of less than 1.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: July 28, 2015
    Assignee: LORD Corporation
    Inventor: Russell A. Stapleton
  • Patent number: 9086633
    Abstract: A lithographic method is disclosed that includes, on a substrate provided with a layer of a resist and a further layer of a material provided on the layer of resist, providing a pattern in the further layer, the pattern defining a space via which an area of the layer of resist may be exposed to radiation, a distance between features of the pattern defining the space, and exposing the layer of resist to radiation having a wavelength greater than the distance between features of the pattern defining the space, such that near-field radiation is generated which propagates into and exposes an area of the resist.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: July 21, 2015
    Assignee: ASML HOLDING N.V.
    Inventor: Donis George Flagello
  • Publication number: 20150146180
    Abstract: A method for fabricating a nanoantenna array may include forming a resist layer on a substrate, forming a focusing layer having a dielectric microstructure array on the resist layer, diffusing light one-dimensionally in a specific direction by using a linear diffuser, forming an anisotropic pattern on the resist layer by illuminating the light diffused by the linear diffuser on the focusing layer and the resist layer, depositing a material suitable for a plasmonic resonance onto the substrate and the resist layer on which the pattern is formed, and forming a nanoantenna array on the substrate by removing the resist layer and the material deposited on the resist layer. A light diffusing angle by the linear diffuser and a size of the dielectric microstructure are determined based on an aspect ratio of the pattern to be formed.
    Type: Application
    Filed: April 15, 2014
    Publication date: May 28, 2015
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kyeong Seok LEE, Won Mok KIM, Taek Sung LEE, Wook Seong LEE, Doo Seok JEONG, Inho KIM
  • Patent number: 9040227
    Abstract: A microstructure manufacturing method includes forming a layer of a photosensitive resin on a substrate surface having an electrical conductivity, forming a structure of the photosensitive resin by exposing the layer of the photosensitive resin to light and developing the layer of the photosensitive resin to expose a part of the substrate surface, forming a first plated layer on the exposed part of the substrate surface by soaking the structure of the photosensitive resin in a first plating solution, curing the structure of the photosensitive resin after forming the first plated layer, removing at least part of the first plated layer after curing the structure of the photosensitive resin, and forming a second plated layer on a part where the first plated layer is removed, by soaking the structure of the photosensitive resin in a second plating solution different from the first plating solution.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Teshima, Yutaka Setomoto
  • Publication number: 20150140729
    Abstract: A method of making a structure having a patterned a base layer and useful in the fabrication of optical and electronic devices including bioelectronic devices includes, in one embodiment, the steps of: a) providing a layer of a radiation-sensitive resin; b) exposing the layer of radiation-sensitive resin to patterned radiation to form a base layer precursor having a first pattern of exposed radiation-sensitive resin and a second pattern of unexposed radiation-sensitive resin; c) providing a layer of fluoropolymer in a third pattern over the base layer precursor to form a first intermediate structure; d) treating the first intermediate structure to form a second intermediate structure; and e) selectively removing either the first or second pattern of resin by contacting the second intermediate structure with a resin developing agent, thereby forming the patterned base layer.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: Marc FERRO, George MALLIARAS