Radiation Mask Patents (Class 430/5)
  • Patent number: 9753366
    Abstract: The invention relates to a method for determining at least one unknown laser beam parameter of a laser beam used for correcting errors of a transparent material including inducing a first persistent modification in the material by an interaction with the laser beam having a first set of laser beam parameters, measuring the induced first persistent modification of the material, calculating a second persistent modification in the material using a model describing persistent modifications in the material with a second set of laser beam parameters, wherein the first set of laser beam parameters comprises the second set of laser beam parameters and the at least one unknown laser beam parameter, setting up a target functional including the first persistent modification and the second persistent modification, and determining the at least one unknown laser beam parameter by minimizing the target functional.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 5, 2017
    Assignee: Carl Zeiss SMS Ltd.
    Inventor: Vladimir Dmitriev
  • Patent number: 9754068
    Abstract: A method includes providing a layout of a portion of a photomask. The layout includes a plurality of target features having a shape in accordance with a corresponding one of a target shape. For each of the target shapes, a local map specifying a respective value of a local sub-resolution assist feature (SRAF) usefulness for each of a plurality of positions relative to the target shape is provided. For each of the target features, an assignment of a part of the values of the local SRAF usefulness of the local map for the target shape corresponding to a target feature to a position relative to the portion of the photomask is provided. A global map specifying a global SRAF usefulness for each of the positions relative to the portion of the photomask is provided on the basis of the assignment of the values of the local SRAF usefulness.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Andrey Lutich
  • Patent number: 9754071
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco
  • Patent number: 9753365
    Abstract: The present disclosure provides a mask plate, belongs to the field of display technology, and can maintain a uniform exposing interval, so that the exposure pattern has a uniform deformation amount and pattern size. A mask plate comprises opaque regions and transparent regions, and spacers of the same height are arranged in the opaque regions. Another mask plate comprises active regions and dummy regions, and spacers of the same height are arranged in the dummy regions. The present disclosure can be applied in a process for fabricating a color film substrate.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 5, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Bing Lu
  • Patent number: 9747401
    Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Ayman Hamouda
  • Patent number: 9746764
    Abstract: A mask blank, including: a thin film for forming a transfer pattern; a resist underlying film made of a resist underlying composition and provided on the thin film; a resist film made of a chemically amplified resist and provided on the resist underlying film; and a mixture film provided so as to be interposed between the resist underlying film and the resist film, wherein the resist underlying film is configured so that a molecular weight is reduced from the thin film side to the resist film side in a thickness direction, and has a low molecular weight region in which the molecular weight is low on the resist film side surface, and the mixture film is formed by mixing a component of the low molecular weight region and a component of the chemically amplified resist.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 29, 2017
    Assignees: HOYA CORPORATION, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Takahiro Hiromatsu, Masahiro Hashimoto, Yasushi Sakaida, Ryuta Mizuochi, Rikimaru Sakamoto, Masaki Nagai
  • Patent number: 9746780
    Abstract: A maskless exposure device includes an exposure head including a digital micro-mirror device and an exposure source, the digital micro-mirror device being configured to reflect a source beam outputted from the exposure source to a substrate and a system controller configured to control the digital micro-mirror device by using a graphic data system file. The graphic data system file includes data regarding patterns to be formed on the substrate. A pattern extending in a direction parallel to a scan direction of the exposure head includes a first pattern portion having a first width that is greater than a target width and a second pattern portion alternately disposed with the first pattern portion and having a second width that is less than the target width.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Seok Kim, Sang-Hyun Yun, Hi-Kuk Lee, Jae-Hyuk Chang, Sang-Hyun Lee, Jung-In Park, Jung-Chul Heo, Kab-Jong Seo, Ki-Beom Lee, Jun-Ho Sim
  • Patent number: 9748148
    Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 29, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ellie Y. Yieh, Huixiong Dai, Srinivas D. Nemani, Ludovic Godet, Christopher Dennis Bencher
  • Patent number: 9746763
    Abstract: Provided is a phase shift mask including a substrate, a phase shift layer, and a shielding layer. The phase shift layer is located on the substrate. A pattern of the phase shift layer includes a main pattern and sub-resolution assist features (SRAFs). The SRAFs are disposed around the main pattern. The phase shift layer has a transmission, and the transmission is larger than 6%. The shielding layer at least covers the SRAFs of the phase shift layer.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 29, 2017
    Assignee: Winbond Electronics Corp.
    Inventor: Kao-Tun Chen
  • Patent number: 9739722
    Abstract: A process for inspecting an EUV mask blank capable of distinguishing phase defects and amplitude defects and capable of detecting small amplitude defects, a process for producing an EUV mask blank using the inspection process, and an EUV mask blank obtainable by such a process. A process for inspecting a reflective mask blank for EUV lithography having a multilayer reflective film and an absorber layer. The process includes a first step of detecting in-plane defects in the multilayer reflective film by applying EUV light to the surface of the multilayer reflective film, a second step of detecting in-plane defects from the absorber layer by applying light having a wavelength of from 150 to 600 nm to the surface of the absorber layer, and a step of distinguishing phase defects and amplitude defects in the reflective mask blank by comparison between the first and second in-plane defect data.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 22, 2017
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroshi Nakanishi, Junichi Kageyama, Yoshiaki Ikuta
  • Patent number: 9741828
    Abstract: The present invention discloses a mask, a manufacturing method thereof and a manufacturing method of a thin film transistor. The mask includes: a first substrate and phase shift patterns formed above the first substrate, wherein an opening area is formed between the adjacent phase shift patterns and a halftone pattern is formed at positions corresponding to the phase shift patterns and the opening area. In the present invention, when an active layer pattern, a source and a drain are formed through one patterning process by using the mask, the design of narrow channel of the thin film transistor can be realized. As the width of the channel region of the thin film transistor becomes narrow, the volume of the thin film transistor can be effectively reduced, and the super-miniaturization of the thin film transistor can be achieved.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 22, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Rui Xu
  • Patent number: 9741564
    Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 22, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Setta, Taketo Kuriyama, Nobuhiro Komine
  • Patent number: 9740093
    Abstract: A pellicle is proposed in which a mask-bonding agglutinant layer, that bonds the pellicle to a photomask, is divided into segments, and the vacancies thus created between these segments are entirely occupied by segments of a non-resilient body layer, and these alternately arranged segments are flush with each other.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 22, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Kazutoshi Sekihara
  • Patent number: 9735023
    Abstract: Disclosed herein is a composition comprising a first block copolymer that comprises a first block and a second block; where the first block has a higher surface energy than the second block; a second block copolymer that comprises a first block and a second block; where the first block of the first block copolymer is chemically the same as or similar to the first block of the second block copolymer and the second block of the first block copolymer is chemically the same as or similar to the second block of the second block copolymer; where the weight percent based on total solids of the first block of the second block copolymer is greater than that of the first block of the first block copolymer; where the first block copolymer phase separates into a first morphology of cylindrical or lamellar domains when disposed singly on a substrate.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 15, 2017
    Assignees: DOW GLOBAL TECHNOLOGIES LLC, ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Jieqian Zhang, Phillip D. Hustad, Peter Trefonas, III, Mingqi Li, Valeriy V. Ginzburg, Jeffrey D. Weinhold
  • Patent number: 9733562
    Abstract: An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9734572
    Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
  • Patent number: 9733569
    Abstract: A mask includes a transparent substrate and a light blocking pattern. The light blocking pattern includes a light blocking part and a diffraction pattern. The light blocking part is disposed on the transparent substrate and is configured to block light. The diffraction pattern includes a plurality of protrusion parts and is configured to diffract the light. The plurality of protrusion parts protrudes from a side of the blocking part and is separated from each other.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Son, Min Kang, Bong-Yeon Kim, Hyun-Joo Lee, Jin-Ho Ju
  • Patent number: 9735011
    Abstract: A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via. The method also includes aligning the reticle with the semiconductor substrate with the conductive via to align the scattering bar next to the conductive via; and forming metal line patterns on the first dielectric layer and a top surface of the conductive via to completely cover the conducive via.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Baojun Zhao
  • Patent number: 9726972
    Abstract: A mask blank wherein damage to a light semitransmissive film due to dry etching for removing a light shielding film is inhibited. Mask blank 100 has a light semitransmissive film 2 and light shielding film 4 laminated on a main surface of a transparent substrate 1. Film 2 can be dry etched with a fluorine-based gas. Film 4 has laminated lower layer 41 and upper layer 42. Lower layer 41 contained tantalum and id substantially free from hafnium, zirconium, and oxygen. Upper layer 42 contains tantalum and one or more of hafnium and zirconium and is substantially free from oxygen excluding the surface layer of the upper layer 42. Between the light semitransmissive film 2 and lower layer 41 is an etching stopper film 3 having etch selectivity with respect to the lower layer 41 in dry etching with an etching gas containing the chlorine-based gas and no oxygen gas.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 8, 2017
    Assignee: HOYA CORPORATION
    Inventors: Hiroaki Shishido, Ryo Ohkubo, Osamu Nozawa
  • Patent number: 9720316
    Abstract: A mask blank for EUV lithography (EUVL) excellent in in-plane uniformity of the peak reflectivity of light in the EUV wavelength region and in in-plane uniformity of the center wavelength of reflected light in the EUV wavelength region, at the surface of a multilayer reflective film, and a process for its production, as well as a substrate with reflective layer for EUVL to be used for the production of such a mask blank for EUVL, and a process for its production. A substrate with reflective layer for EUVL having a reflective layer for reflecting EUV light formed on a substrate, where the reflective layer is a multilayer reflective film having a low refractive index layer and a high refractive index layer alternately stacked plural times.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 1, 2017
    Assignee: Asahi Glass Company, Limited
    Inventor: Masaki Mikami
  • Patent number: 9715175
    Abstract: A reticle protection device capable of keeping a reticle therein is provided with an inner pod capable of keeping the reticle therein; an outer pod capable of keeping the inner pod therein; an electroconductive movable contact portion provided on at least one of the inner pod and the outer pod and being capable of coming into contact with an electroconductive film of the reticle; and a leaf spring for achieving electric conduction of the contact portion to at least one of the inner pod and the outer pod. The reticle is kept in the inner pod and the inner pod is kept in the outer pod, thereby enabling stable grounding of the reticle.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 25, 2017
    Assignee: NIKON CORPORATION
    Inventor: Kazuya Ota
  • Patent number: 9715569
    Abstract: Disclosed are techniques for devising an electronic design with disconnected field domains. These techniques identify a plurality of electrically conductive shapes of an electronic design, add a plurality of patches to a model of the electronic design for multiple apertures in the electronic design, analyze the model to generate analysis results for the electronic design, and devise or implement the electronic design based in part or in whole upon the analysis, wherein an aperture of the multiple apertures causes disconnected electromagnetic field domains in the model.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Xiande Cao, Jian Chen
  • Patent number: 9715170
    Abstract: Provided are an optical proximity correction (OPC) method capable of correcting a slit-effect in an extreme ultraviolet (EUV) exposure process and a method of manufacturing an EUV mask by using the OPC method. The OPC method includes, dividing a transmission cross coefficient (TCC) according to regions of a slit that is used in an EUV exposure process, generating OPC models reflecting the TCCs that are divided, and correcting the OPC method.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Jang, Sang-hwa Lee
  • Patent number: 9709905
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Hsin-Chieh Yao, Tien-I Bao
  • Patent number: 9709885
    Abstract: A method for manufacturing a photomask blank having at least a silicon-containing inorganic film over a transparent substrate includes forming the silicon-containing inorganic film such that a surface has an oxygen concentration not less than 55 atomic percent and not more than 75 atomic percent, the silicon-containing inorganic film being an SiO film or an SiON film and serving as a hard mask film.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 18, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Takashi Yoshii, Toyohisa Sakurada, Akira Ikeda, Hideo Kaneko, Satoshi Watanabe, Yoshio Kawai
  • Patent number: 9709481
    Abstract: A method determines the tack of a material placed in contact with a surface. A sample is provided of the material, the sample including a sheet whose width increases from a first narrow end to a second wide end. The sample is applied to an upwards facing supporting surface of plate. The sample is compacted against the supporting surface of plate and a weight is attached to the first end of the sample. The plate is turned over in such a way that the supporting surface faces downwards. The detachment of the sample from the supporting surface is measured in terms of distance detached from the first end of the sample as a function of time.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: July 18, 2017
    Assignee: ALENIA AERMACCHI S.p.A.
    Inventor: Stefano Giuseppe Corvaglia
  • Patent number: 9709884
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over the substrate. A capping layer is disposed over the reflective structure. An absorber layer is disposed over the capping layer. The absorber layer contains a material that has a refractive index in a range from about 0.95 to about 1.01 and an extinction coefficient greater than about 0.03.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9703188
    Abstract: A pellicle is proposed in which the agglutinant layer which enable the pellicle to be adhered to a photomask is doped with a mechanoluminescent material so that the uniformness of the thickness of the agglutinant layer can be confirmed, when the pellicle is adhered to the photomask, by observing visually or by CCD camera for any irregularity in the pattern of the light emitted from the agglutinant layer.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 11, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Horikoshi, Yu Yanase
  • Patent number: 9703187
    Abstract: The present invention addresses the problem of providing a pellicle which has high EUV transmittance and high strength, while being not susceptible to damage by heat. In order to solve the above-mentioned problem, the present invention provides a pellicle which comprises a pellicle film that has a refractive index (n) of light having a wavelength of 550 nm of 1.9-5.0 and a pellicle frame to which the pellicle film is bonded. The pellicle film has a composition that contains 30-100% by mole of carbon and 0-30% by mole of hydrogen. The intensity ratio of the 2D-band to the G-band, namely (intensity in 2D-band)/(intensity in G-band) is 1 or less, or alternatively, the intensity in the 2D-band and the intensity in the G-band are 0 in the Raman spectrum of the pellicle film.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 11, 2017
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Yosuke Ono, Kazuo Kohmura
  • Patent number: 9696649
    Abstract: An optical head includes a lens array including resin lenses, a holder that holds the lens array, and a positioning mechanism that positions the holder such that the holder is opposed to a target. The positioning mechanism is configured to change a distance between the lens array and the target depending on a change in at least any one of temperature and humidity.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 4, 2017
    Assignee: Oki Data Corporation
    Inventor: Taishi Kaneto
  • Patent number: 9697325
    Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
  • Patent number: 9690186
    Abstract: An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML) over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9690191
    Abstract: A method for repairing a defect on a substrate surface includes placing on the defect a nanoparticle that includes a conductive material. A region of the substrate surface in which the nanoparticle is placed is irradiated, the region being larger than the nanoparticle. An energy density of the irradiation is below a modification threshold for the substrate surface.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: June 27, 2017
    Assignee: Carl Zeiss SMS Ltd.
    Inventors: Sergey Oshemkov, Vladimir Kruglyakov
  • Patent number: 9684234
    Abstract: Simplified methods of multiple-patterning photolithography using sequential infiltration synthesis to modify the photoresist such that it withstands plasma etching better than unmodified resist and replaces one or more hard masks and/or a freezing step in MPL processes including litho-etch-litho-etch photolithography or litho-freeze-litho-etch photolithography.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 20, 2017
    Assignee: UCHICAGO ARGONNE, LLC
    Inventors: Seth B. Darling, Jeffrey W. Elam, Yu-Chih Tseng
  • Patent number: 9665010
    Abstract: In a method for operating a microlithographic projection exposure apparatus, a facet mirror is illuminated with projection light having a center wavelength of between 5 nm and 30 nm. The facet mirror has a plurality of adjustable mirror facets, wherein groups of adjacent mirror facets form regions which are imaged by an optical unit onto an object plane of a projection objective of the projection exposure apparatus. There the images of the regions are superimposed in an object field. An illumination field, which is identical to the object field or a part thereof, is illuminated with the projection light. A mask containing structures to be imaged is moved in the object plane of the projection objective in such a way that the illumination field scans over the mask. According to the invention, during step c) the size of the illumination field is varied by adjusting at least one mirror facet.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 30, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventor: Markus Deguenther
  • Patent number: 9664997
    Abstract: Methods of manufacturing a mask blank and a transfer mask that reduce internal stress of a thin film. The methods include preparing a transparent substrate having a pair of opposing main surfaces and composed of a glass material having a hydrogen content of less than 7.4×1018 molecules/cm3, forming a thin film composed of a material containing silicon or metal on one of the main surfaces of the transparent substrate, and carrying out heating treatment or photo irradiation treatment on the transparent substrate with the thin film. The absolute value of a variation of flatness in a predetermined region, as calculated based on a difference in shape obtained from a shape of a main surface of the transparent substrate prior to forming the thin film and a shape of a main surface of the substrate exposed after removing the thin film, is not more than 100 nm.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 30, 2017
    Assignee: HOYA CORPORATION
    Inventors: Atsushi Kominato, Hiroaki Shishido, Osamu Nozawa
  • Patent number: 9664995
    Abstract: Any defects in the reflective coating or absorber layer of an EUV mask are problematic in transferring a pattern of the EUV mask to a wafer since they produce errors in integrated circuit patterns on the wafer. In this regard, a method of manufacturing an EUV mask is provided according to various embodiments of the present disclosure. According to the method of the present disclosure, the defects in the EUV mask can be detected and repaired with an defect-free multilayer body. A substantially defect-free EUV mask can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yuan-Chih Chu
  • Patent number: 9664996
    Abstract: A photomask includes a light transmission substrate having a transfer region and a frame region, a light-transmitting region exposing a portion of the light transmission substrate in the transfer region corresponding to a transfer pattern, and a light-blocking region disposed in the transfer region and surrounding the light-transmitting region, wherein the light-blocking region includes a first light-blocking region surrounding the light-transmitting region, and a second light-blocking region that surrounds the first light-blocking region, and wherein a first light-blocking pattern is disposed on the light transmission substrate in the first light-blocking region, and a plurality of second light-blocking patterns are disposed on the light transmission substrate in the second light-blocking region.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 30, 2017
    Assignee: SK HYNIX INC.
    Inventor: Byung Ho Nam
  • Patent number: 9664999
    Abstract: The present disclosure relates to an extreme ultraviolet (EUV) pellicle having a pellicle film connected to a pellicle frame. In some embodiments, the EUV pellicle has a substrate, and an adhesive material disposed onto the substrate. A pellicle frame is connected to the substrate by way of the adhesive material. The pellicle frame is configured to mount the substrate to an extreme ultraviolet (EUV) reticle.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9658524
    Abstract: A photomask includes: a light blocking member provided on a translucent substrate; a main pattern portion provided in a first region corresponding to a desired pattern, being an opening of the light blocking member; and an auxiliary pattern portion provided in a second region surrounding the position corresponding to the desired pattern and along a side constituting an outline portion of the desired pattern, including a plurality of in-phase auxiliary patterns each of which is an opening transmitting in-phase light with light transmitted through the main pattern portion. The in-phase auxiliary pattern is provided at a distance of ?(2×n×G×?) from the side constituting the outline portion of the desired pattern (where G is a gap length between the photomask and the exposed body, ? is a wavelength of the exposure light, and n is a natural number).
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 23, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Akio Misaka
  • Patent number: 9658522
    Abstract: A reflective extreme ultraviolet (EUV) mask includes a mask substrate, a reflecting layer on an upper surface of the mask substrate, and an absorbing layer pattern on an upper surface of the reflecting layer, the absorbing layer pattern having an exposing region and a peripheral region, and the absorbing layer pattern including a grating pattern in the peripheral region to reduce reflectivity of light incident on the peripheral region.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyun Kim, Dong-Wan Kim, Chang-Min Park, In-Sung Kim, Dong-Gun Lee
  • Patent number: 9658531
    Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Guoxiang Ning, Chunyu Wong, Paul Ackmann, Sarasvathi Thangaraju
  • Patent number: 9658526
    Abstract: A pellicle mask assembly includes a mask, a pellicle frame, and a pellicle membrane. The pellicle frame has a bottom side attached to the mask, and a top side covered by the pellicle membrane. The pellicle frame includes a coating on its inner surface and the coating is configured to monitor a change of environment inside the pellicle mask assembly. In embodiments, the change of environment includes increased humidity and/or increased chemical ion density inside the pellicle mask assembly. Methods of making and using the pellicle mask assembly are also disclosed.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Wen Lin, Sheng-Chi Chin, Ting-Hao Hsu, Tzu-Ting Chou, Shu-Hsien Wu
  • Patent number: 9651857
    Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Ta-Cheng Lien, Anthony Yen
  • Patent number: 9651858
    Abstract: A binary photomask blank has a light-shielding film on a transparent substrate, the light-shielding film composed mainly of transition metal M and Si, or M, Si and N, and having an optical density of at least 3.0. The light-shielding film includes a layer containing M, Si and N so as to meet the formula: B?0.68×A+0.23 wherein A is an atomic ratio M/Si and B is an atomic ratio N/Si, and has a thickness of up to 47 nm. The binary photomask blank has a thin light-shielding film capable of fully shielding exposure light.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 16, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Takuro Kosaka, Kazuhiro Nishikawa
  • Patent number: 9651855
    Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 16, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Lei Sun, Wenhui Wang, Ryan Ryoung-Han Kim
  • Patent number: 9646220
    Abstract: A method of determining an average contour of a patterned feature on a wafer includes providing a reference contour corresponding to the patterned feature on the wafer, providing a plurality of images of the patterned feature, extracting from the plurality of images a plurality of extracted contours that represent the patterned feature, eliminating flyers from the plurality of extracted contours, and generating the average contour of the patterned feature based on the extracted contours remaining after elimination of the flyers.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Francois Weisbuch
  • Patent number: 9645485
    Abstract: A halftone phase shift photomask blank comprising a transparent substrate and a halftone phase shift film consisting of silicon, nitrogen and optional oxygen, and providing a phase shift of 150°-200° relative to light of wavelength up to 200 nm. The phase shift film includes at least one layer meeting the formula: 2×O/Si+3×N/Si?3.5 wherein Si is a silicon content (at %), N is a nitrogen content (at %), and O is an oxygen content (at %). The phase shift film exhibits satisfactory in-plane uniformity of transmittance.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 9, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takuro Kosaka, Yukio Inazuki, Hideo Kaneko, Toyohisa Sakurada
  • Patent number: 9646934
    Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shijie Wang, Yong Feng Fu, Siew Yong Leong, Lei Wang, Alex See
  • Patent number: RE46464
    Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 4, 2017
    Assignee: Lam Research Corporation
    Inventors: Qian Fu, Ce Qin, Hyun-Yong Yu