Abstract: The present application provides a method of fabricating a light-emitting diode (LED) display panel, including the following steps: forming an LED substrate including a first substrate, an LED chip disposed on the first substrate, and a first electrode disposed on the LED chip; forming a driving substrate including a second substrate and a second electrode disposed on the second substrate; activating surfaces of the first electrode and the second electrode; aligning and pre-bonding the first electrode with the second electrode; and bonding the first electrode and the second electrode.

Abstract: A structure of a substrate is provided for application in an electric power module. The substrate includes element regions, on which a plurality of semiconductor elements are arranged, a center region that defines a space among the element regions, an input terminal region, on which an input terminal for applying an electric current to the substrate is disposed, and one or more slit insulation portions that are defined to face toward sides, respectively, of the element regions adjacent to the input terminal region, which are among the element regions. The slit insulation portions extend toward the center region in such a manner that an electric current applied through the input terminal region flows into the center region.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Embodiments of methods for processing a semiconductor substrate are described herein. In some embodiments, a method of processing a semiconductor substrate includes removing material from a backside of a reconstituted substrate having a plurality of dies to expose at least one die of the plurality of dies; etching the backside of the reconstituted substrate to remove material from the exposed at least one die; and depositing a first layer of material on the backside of the reconstituted substrate and the exposed at least one die.

Abstract: A semiconductor package structure includes a package substrate, an encapsulant, at least one passage and at least one semiconductor element. The encapsulant is disposed on the package substrate and has a peripheral surface, and includes a first encapsulant portion and a second encapsulant portion spaced apart from the first encapsulant portion. The at least one passage is defined by the first encapsulant portion and the second encapsulant portion, and the passage has at least one opening in the peripheral surface of the encapsulant. The at least one semiconductor element is disposed on the package substrate and exposed in the passage.

Abstract: A display device includes a substrate, a thin film transistor disposed on the substrate, and a display element electrically connected to the thin film transistor. The substrate includes a first substrate layer, a second substrate layer disposed on the first substrate layer, a first barrier layer disposed between the first substrate layer and the second substrate layer, and a first ultraviolet light blocking layer disposed between the first substrate layer and the second substrate layer.

Abstract: A pixel array substrate has a plurality of sub-pixel regions, wherein a pixel structure of an individual sub-pixel region includes a first signal line, a second signal line, a first contact pad, a second contact pad, a light-emitting diode, a first conductive structure, and a flux structure layer. The first contact pad and the second contact pad are respectively electrically connected with the first signal line and the second signal line. The light-emitting diode is disposed on the first contact pad. A portion of the first conductive structure is disposed between the first contact pad and a first electrode of the light-emitting diode. The flux structure layer partially surrounds the first conductive structure and the light-emitting diode. A top portion of the flux structure layer is higher than a top surface of the first electrode and is lower than a bottom surface of a light-emitting layer of the light-emitting diode.

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.

Abstract: An electronic component module includes a first substrate mounted on an upper surface of a second substrate such that at least a portion of a lower surface of the first substrate is exposed externally of the second substrate and electronic devices mounted on the first substrate and the second substrate, including at least one electronic device mounted on the upper surface of the second substrate.

Abstract: The present disclosure provides a package device and a method of manufacturing the same. The package device includes a supporting member, a main component, a sealant, and a conductive encapsulant. The supporting member includes a plurality of grounding contacts. The main component is mounted on the supporting member. The sealant covers the main component. The conductive encapsulant encases the sealant and the grounding contacts exposed through the sealant for EMI shielding.

Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.

Abstract: The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

Abstract: A back plate for rapid and fluid-assisted assembly of micro light emitting elements thereon includes a substrate with a driving circuit, and blocking walls made to protrude from a top surface of the substrate. The top surface of the substrate defines grooves for accommodating and powering micro light emitting elements. Each of the blocking walls semi-surrounds one groove and defines a notch. The notches defined by each blocking wall all face a single direction and the blocking walls and notches impede and gather micro light emitting elements which are made to flow in a fluid suspension and render them much more likely to tumble into the groove. A method for fluid-assisted assembly is also disclosed.

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.

Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and a plurality of core wiring layers disposed on or in the first insulating body, and having a cavity penetrating at least a portion of the first insulating body in a thickness direction of the substrate and including a stopper layer as a bottom surface of the cavity, and an electronic component disposed in the cavity and attached to the stopper layer, and a surface of the stopper layer connected to the electronic component has a composite including at least two among a metal material, an inorganic particle, a filler, and an insulating resin.

Abstract: The disclosure relates to a photocatalytic structure. The photocatalytic structure includes a carbon nanotube structure, a photocatalytic active layer coated on the carbon nanotube structure, and a metal layer including a plurality of nanoparticles located on the surface of the photocatalytic active layer. The carbon nanotube structure comprises a plurality of intersected carbon nanotubes and defines a plurality of openings, and the photocatalytic active layer is coated on the surface of the plurality of carbon nanotubes. The metal layer includes a plurality of nanoparticles located on the surface of the photocatalytic active layer.

Abstract: The electronic card with printed circuit (1) comprises at least one antenna with slots (AT) including a cavity (15) and a metal conductive layer (17) covering the cavity and having a plurality of slots (S17). The slots form openings in the metal conductive layer. In accordance with the invention, the cavity is formed, by removal of material, in the thickness of the printed circuit. The cavity also comprises a metallisation layer (16) on the walls and the metal conductive layer is formed in a plate attached on the electronic card with printed circuit and closes the cavity.

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

Abstract: The present invention relates to a transfer head and a method of manufacturing a micro LED display using the same. In particular, the present invention relates to a transfer head and a method of manufacturing a micro LED display using the same, the transfer head mounting normal micro LEDs on a display substrate without performing a complicated process of sorting out defective micro LEDs from the micro LEDs mounted on the display substrate and replacing the defective micro LEDs with normal micro LEDs.

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad.

Abstract: A printed circuit board assembly includes a first printed circuit board, a second printed circuit board disposed on the first printed circuit board and including an antenna pattern, a third printed circuit board disposed on the first printed circuit board, one or more first electronic components disposed between the first and the second printed circuit board and electrically connected to at least one of the first and the second printed circuit board, one or more second electronic components disposed between the first and the third printed circuit board, and electrically connected to at least one of the first and the third printed circuit board, a first interposer substrate electrically connecting the first printed circuit board and the second printed circuit board to each other, and a second interposer substrate electrically connecting the first printed circuit board and the third printed circuit board to each other.

Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.

Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.

Abstract: A package structure includes a first die, a second die, a bridge, an encapsulant and a redistribution layer (RDL) structure. The bridge is arranged side by side with the first die and the second die. The encapsulant laterally encapsulates the first die, the second die and the bridge. The RDL structure is disposed on the first die, the second die, the bridge and the encapsulant. The first die and the second die are electrically connected to each other through the bridge and the RDL structure.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.

Abstract: An apparatus including a dot matrix transfer head that includes an impact wire housing. A plurality of impact wires are disposed within the impact wire housing and extend out of the impact wire housing. A splaying element attached to a bottom surface of the impact wire housing. The plurality of impact wires extend into and through the splaying element. A guide head attached to a bottom surface of the splaying element. The guide head includes multiple holes that arrange the plurality of impact wires in a matrix configuration. The splaying element is designed to direct the plurality of impact wires toward the multiple holes in the guide head.

Abstract: Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.

Abstract: A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.

Abstract: There is provided a display device. The display device includes a plurality of semiconductor elements disposed on a substrate; a plurality of LEDs disposed on the plurality of semiconductor elements and electrically connected to the plurality of semiconductor elements, respectively; and a plurality of reflectors disposed above the semiconductor elements and each located between every two of the LEDs. The plurality of LEDs may include a plurality of light-emitting layers disposed on the plurality of semiconductor elements, and a common electrode disposed on the plurality of light-emitting layers. The reflectors are disposed between the LEDs, so that light emitted from LEDs does not travel toward the side portions of the LEDs but toward the above of the substrate, thereby improving the light extraction efficiency and suppressing color mixture.

Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Abstract: To provide a novel display panel that is highly convenient or reliable. To provide a novel input and output device that is highly convenient or reliable. To provide a novel data processing device that is highly convenient or reliable. To provide a method for manufacturing a novel display panel that is highly convenient or reliable. The display panel includes a pixel, a third conductive film electrically connected to the pixel, an insulating film including an opening portion overlapping with the third conductive film, and an electrode including a first region in contact with the third conductive film and a second region functioning as a contact point.

Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

Abstract: A micro-LED transfer method and manufacturing method. The micro-LED (303) transfer method comprises: bringing pickup units (305) of a transfer head in contact with micro-LEDs (303) on a carrier substrate (301), wherein the pickup units (305) are able to apply current to the micro-LEDs (303); applying current to the micro-LEDs (303) via the pickup units (305) to heat up bonding layers (302) between the micro-LEDs (303) and the carrier substrate (301) to be melted; picking up the micro-LEDs (303) from the carrier substrate (301) with the transfer head; bonding the micro-LEDs (303) onto a receiving substrate (307); and removing the transfer head from the micro-LEDs.

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

Abstract: A semiconductor device die transfer apparatus includes a first frame to hold a wafer tape having a plurality of semiconductor device die disposed on a side of the wafer tape and a second frame to secure a product substrate having a circuit trace thereon. The second frame is configured to secure the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device die on the wafer tape. Additionally, a rotary transfer collet is disposed between the wafer tape and the product substrate. The rotary transfer collet has a rotational axis allowing rotation from a first position facing the wafer tape to pick a die of the plurality of semiconductor device die to a second position facing the circuit trace on the product substrate to release the die, thereby applying the die directly on the product substrate during a transfer operation.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Abstract: A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.

Abstract: Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.