Abstract: A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end.

Abstract: The present invention provides a process for producing a wiring circuit board which can be inhibited from developing whiskers and can be reduced in the unevenness of connectivity with electronic parts while retaining the connectivity. According to the present invention, a wiring pattern 12 comprising a thin metal film 31 and a conductor layer 33 is formed on a base insulating layer BIL. A tin-plated layer 34 is formed by electroless plating so as to coat the wiring pattern 12 therewith. The wiring pattern 12 and the tin-plated layer 34 are then subjected to a heat treatment. The heat treatment temperature and heat treatment period are regulated to 175 to 225° C. and 2 to 10 minutes, respectively. By the heat treatment, a mixture layer 35 comprising copper and tin is formed. Thereafter, a solder resist SOL is formed over the base insulating layer so as to cover the wiring pattern 12 and tin-plated layer 34 in given regions. Subsequently, the solder resist SOL is subjected to a heat curing treatment.

Abstract: A semiconductor device includes a plurality of semiconductor packages each with a semiconductor element and a flexible board. The flexible board is wider than the semiconductor element and is electrically connected to the semiconductor element. The plurality of semiconductor packages are stacked on one surface of a mother board. The semiconductor element is positioned between the flexible boards of the semiconductor packages in adjacent layers. The flexible boards in the adjacent layers are joined together at junction portions positioned at a part of the flexible boards which sticks out from an area in which the semiconductor elements and the flexible boards overlap. A reinforcing resin is provided in at least a part of the area between the flexible boards in the adjacent layers and between the junction portion of the flexible boards and the corresponding semiconductor element. The reinforcing resin contacts at least a part of the adjacent flexible board.

Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: An apparatus including a first die mounted on a primary side of an electronic package and a second die mounted on a secondary side of the electronic package between the electronic package and a printed circuit board. The apparatus further comprising a thermal component thermally connected to the second die and mounted on the printed circuit board, the thermal component comprising a set of pins extending from a heat sink through a set of through-holes in the printed circuit board. A method including positioning a set of thermal connectors through a printed circuit board, the thermal connectors extending from a primary side of the printed circuit board to a secondary side of the printed circuit board opposite the primary side. The method further including thermally connecting the thermal connectors to a die positioned between an electronic package and the primary side of the printed circuit board to transfer heat from the die to the secondary side of the printed circuit board.

Abstract: A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.

Abstract: The invention relates to a power semiconductor module comprising at least one power semiconductor chip, and comprising a pressure apparatus which exerts a pressure on the top side of the power semiconductor chip when the power semiconductor module is fixed to a heat sink. In addition, a bonding wire which is arranged distant from the pressure element, is bonded to the top side. The invention also relates to methods for fabricating a power semiconductor module, and for fabricating a power semiconductor arrangement comprising a power semiconductor module and a heat sink.

Abstract: A semiconductor device includes a first semiconductor device and a second semiconductor device. Through-holes in the second semiconductor device extend from an upper side of the second semiconductor device adjacent contact pads to a bottom side of the second device. Tower contact bumps are electrically connected to contact pads of the first semiconductor device. The second semiconductor device is arranged adjacent the first semiconductor device so that the tower contact bumps are disposed within the through-holes and are electrically connected with contact pads of the second semiconductor device.

Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

Abstract: A semiconductor device and method for manufacturing. One embodiment includes a carrier, a structured layer arranged over the carrier and a semiconductor chip applied to the structured layer. The structured layer includes a first structure made of an elastic material and a second structure made of an adhesive material.

Abstract: A method of manufacture of an electronic substrate, having a process of embedding electronic components in a substrate, and a process of ejecting liquid droplets containing a conductive material, to form a wiring pattern connected to the external connection electrodes of the electronic components embedded in the substrate.

Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.

Abstract: Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a leadframe, and a third portion disposed between the first and second portions. During a molding process, the third portion is compressively strained to impart forces to the first and second portions that maintain these portions in contact with the conductive regions of the die and leadframe. After the molding material sets, the third portion remains in a state of compressive strain, and imparts forces on the first and second portions that maintain the electrical connections. The spring structure may be made of less expensive materials, and does not require cleaning, fluxing, or reflowing, thereby reducing manufacturing cost and time.

Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.

Abstract: In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduce, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.

Abstract: The present invention relates to a method of manufacturing a device having a flexible substrate and a device having a flexible substrate manufactured using the method. According to the method of manufacturing a device having a flexible substrate of the invention, glass is used as a mother substrate, a polymer layer, which is used as a substrate, is formed on the mother substrate using a chemical vapor deposition method or a vacuum evaporation method, a device is formed, and finally, the substrate where the device is formed is separated from the mother substrate, such that a large-scale device having a flexible substrate can be manufactured. Further, as a substrate forming an organic light emitting device and a sealant are formed of the same material, the device is not bent due to stress generated from the device itself after the device is manufactured.

Abstract: A mass storage device includes a probe that has a cantilever having a first end region operatively connected to a substrate and a second end region rotated in a direction such that the second end region is opposed to the first end region. A tip is disposed on the second end region, with the tip pointing in a direction opposed to the first end region.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.

Abstract: A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of integrated circuits on the circuit side, and a plurality of substrate contacts on the circuit side in electrical communication with the integrated circuits. The method also includes the steps of forming vias from the back side to the substrate contacts, forming a conductive layer in the vias and on the back side in electrical contact with the substrate contacts; and forming the conductive layer on the back side into a plurality of conductors in electrical communication with the substrate contacts. The semiconductor component includes the semiconductor substrate, the through interconnects and the redistribution conductors. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact.

Abstract: This invention relates to a high thermal conductivity composite material which comprises diamond particles and a copper matrix useful as electronic heat sinks for electronics parts, particularly for semiconductor lasers, high performance MPUs (micro-processing units), etc., also to a process for the production of the same and a heat sink using the same. According to the high thermal conductivity diamond sintered compact of the present invention, in particular, there can be provided a heat sink having a high thermal conductivity as well as matching of thermal expansions, most suitable for mounting a large sized and high thermal load semiconductor chip, for example, high output semiconductor lasers, high performance MPU, etc. Furthermore, the properties such as thermal conductivity and thermal expansion can freely be controlled, so it is possible to select the most suitable heat sink depending upon the features and designs of elements to be mounted.

Abstract: An apparatus for connecting at least two components contains a lower die and an upper die. The lower die has the components which are to be connected, with the first component supporting the at least second component with an at least partial overlap relative to the first component. The lower die and the upper die can be moved relative to one another. The upper die carries at least two heatable plungers which are connected so as to be able to move relative to one another via a sealed pressure pad. The plungers and the pressure pad have a first flexible layer between them. A second flexible layer is arranged between the upper die and the lower die.

Abstract: A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a socket having detachment mechanisms, a second process of pressing the bump electrodes against the pads by weighting the semiconductor integrated circuit device, and a third process of detaching the bump electrodes from the pads by exerting force on the semiconductor integrated circuit device in a direction opposite to a weighting direction of the second process. Automatic insertion and detachment of a semiconductor integrated circuit chip in a burn-in test is facilitated by detaching the bump electrodes from the pads by pushing up the semiconductor integrated circuit device.

Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.

Abstract: A method for assembling a power module includes providing a casing with a plurality of receiving elements. At least one substrate carrying at least one semiconductor chip is provided within the casing. At least one support element is provided. An elastically stressed cover is arranged over the at least one support element, and the cover is released so that the elastically stressed cover is restrained by the at least one support element and the plurality of receiving elements.

Abstract: An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the contacting portions correspondingly; at least one restricting structure which restricts the chip module to move a distance relative to the substrate depending on the compression deformation of the terminals when the terminals are contacted with the contacting portions; and at least one elastic element just producing deformation when the chip module moves the distance. When the terminals are compressed and contacted with the contacting portions, the restricting structure restricts the chip module to move the distance depending on the compression deformation of the terminals, so that the elastic element just produces deformation, which make the chip module only move in the direction opposite to the deformation direction of the terminals.

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

Abstract: A power semiconductor module comprising a housing of a first plastic, at least one substrate carrier with a circuit constructed thereon and electric terminating elements extending therefrom. The housing includes attachment means for its permanent connection with the substrate carrier. The housing has a permanently elastic sealing device of a second plastic which is formed integrally with the housing and encircles and is directed towards a first inner main surface of the substrate carrier. A method for constructing such a module includes the steps of constructing a housing of a first mechanically stable plastic and a sealing device of a second permanently elastic plastic; disposing the at least one substrate carrier on the housing; and permanently connecting the housing to the substrate carrier.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: An IC chip package and related method are disclosed. The IC chip package may include a printed circuit board (PCB) coupled to a chip carrier by a land grid array (LGA) connector; a metal stiffener including at least one force-adjustable member contacting an underside of the PCB; and at least two couplers for coupling the metal stiffener to a lid or a heat sink, with the PCB, the chip carrier and the LGA connector therebetween. The force-adjustable member reduces the required assembly forces and accommodates natural and non-systematic out-of flatness tolerances of the PCB and the chip carrier.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible layer wherein a slurry containing a plurality of elements with circuit elements thereon washes over the flexible layer and slides into recessed regions or holes found in the flexible layer. Interconnect is then deposited thereon. In another embodiment, interconnect is placed on the flexible layer followed by a slurry containing a plurality of elements.

Abstract: A semiconductor device has a wiring substrate, a semiconductor chip, a conductive bump, and an under-fill resin. The wiring substrate has a solder resist layer, and a stress alleviating portion. The stress alleviating portion is mounted on the solder resist layer opposed to the outer circumference of the semiconductor chip. The material of the stress alleviating portion is different from that of the solder resist layer. The stress alleviating portion alleviates the stress acting on the solder resist layer and the under-fill resin. The semiconductor chip is mounted above the wiring substrate via the conductive bump. The gap between the wiring substrate and the semiconductor chip is filled with the under-fill resin.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A system for providing electrical contacts between a die and an electrical device includes a die and a package. The package includes a first major surface, a second major surface, a first scalloped edge, a second scalloped edge and a solid end adapted for insertion into a slot. The solid end and the scalloped edges carry current greater than the current needed for an input/output signal. The socket includes a base having an opening therein adapted to receive the package. A slot is located at one end of the opening in the base. The slot is provided with a plurality of conductors for carrying currents greater than the current needed for an input/output signal. A first edge and second edge of the opening include a plurality of spaced overhangs positioned over the opening. The overhangs are sloped with respect to the major planar surface.

Abstract: The invention relates to electronic sensors comprising an electromechanical microsensor cell such as a micro-accelerometer, and it more particularly relates to the way in which the microsensor cell per se is mounted in a package that furthermore comprises a printed circuit board carrying the electronic processing circuits associated with the microsensor cell. In order to establish a non-rigid electrical connection between a conductive terminal of the board and a connection pin of the cell, a narrow strip-shaped conductive connection cut by chemical machining from a thin and flexible metal sheet (CuBe) is soldered. The strip comprises at least one circle-arc segment extending over one half-turn or three-fourths of a turn. Its resilience permits very low stiffness in all directions and therefore prevents any transmission of vibrations or shocks to the cell. The manufacture of the connections may be collective for all the connections of a sensor and for successive sensors manufactured serially.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliability and productivity of a semiconductor chip mounting line is enhanced. The invention also provides a method of producing the COF flexible printed wiring board.

Abstract: Embodiments of a micro electro mechanical system are disclosed.

Abstract: The present invention discloses a method for fabricating a quad flat non-leaded package. A lead frame is disposed on a lower mold equipped with a resilient film. The lead frame includes at least a package unit comprising a chip pedestal and a plurality of pins spatially disposed around the chip pedestal. An upper mold corresponding to the lower mold is provided over the lead frame for encapsulation. The upper mold is pressed to form a protrusion from a resilient film between the chip pedestal and the pins, and then the chip pedestal and the pins are encapsulated by a molding material. The resilient film is removed to form a QFN structure with the lead frame protruding from the molding material.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat radiation characteristics and low on-resistance. Moreover, the semiconductor device is provided, which is capable of improving reliability, performing processing in manufacturing processes easily and reducing manufacturing costs. Also, the semiconductor device capable of decreasing the mounting area is provided. A semiconductor chip in which an IGBT is formed and a semiconductor chip in which a diode is formed are mounted over a die pad. Then, the semiconductor chip and the semiconductor chip are connected by using a clip. The clip is arranged so as not to overlap with bonding pads formed at the semiconductor chip in a flat state. The bonding pads formed at the semiconductor chip are connected to electrodes by using wires.

Abstract: A method of manufacturing an optical communication module, and a mold and a lead frame that are suitable for the method are provided. The method comprises the steps of: placing in a mold the lead frame on which a ferrule and an optical communication facility section are mounted; pressing the ferrule by a moving part that can be stopped at a given position relative to the mold (lower mold tool) such that the distal end of the ferrule is positioned at a proper location within the mold; and filling a resin into the mold, wherein a displacement and a reactive force generated in the lead frame when it is pressed are absorbed by springs provided in the lead frame when it is pressed are absorbed by springs provided in the lead frame such that a catching portion for coupling to a connector is formed with high accuracy at a proper position relative the distal end of the ferrule.

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible layer wherein a slurry containing a plurality of elements with circuit elements thereon washes over the flexible layer and slides into recessed regions or holes found in the flexible layer. Interconnect is then deposited thereon. In another embodiment, interconnect is placed on the flexible layer followed by a slurry containing a plurality of elements.

Abstract: A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer of each supporting chip simultaneously with processing to form bond pad caps. The fabrication process requires no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional assembly costs. Further, the standoffs provide improved thermal dissipation for the device and a uniform, stable bonding surface for wire bonding each of the chips to the substrate.

Abstract: A spring contact has a post-release outer upper surface in compression and a post-release outer lower surface in compression. A compressive lower layer of spring material may be formed at a thickness that is three-eighths or less of a tensile upper layer of spring material. A low modulus of elasticity cladding material may also be applied to the outer surface of the spring contact with a lower surface of the cladding material being formed with a compressive stress.

Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.