Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.

Abstract: A method for selectively transferring active components (22) from a source substrate (20) to a destination substrate (10) includes providing a source substrate with one or more active components located on the source substrate, providing a destination substrate, locating a selectively curable adhesive layer (30) between and adjacent to the destination substrate and the source substrate, selecting one or more active components (22A), selectively curing area(s) (32A) of the adhesive layer corresponding to the selected active components to adhere the selected active components to the destination substrate, and removing the source substrate from the destination substrate leaving the selected active components adhered to the destination substrate in the selected areas.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.

Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

Abstract: Forming an embedded electronic component includes attaching an electronic component to a first conductive layer and forming a layer stack with a first partially cured dielectric layer having a first opening and a substrate having a second opening. The partially cured dielectric layer is located over the first conductive layer and the substrate is located over the first partially cured dielectric layer such that the first and second openings surround the electronic component. Heat and pressure are applied to the layer stack such that the first partially cured dielectric layer flows for filling gaps within the first and second openings and becomes fully cured.

Abstract: A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.

Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).

Abstract: A method of manufacturing an electronic device includes the steps of: forming a sacrifice layer made of at least one of an alkali metal oxide and an alkali earth metal oxide in a part of a first substrate; forming a supporting layer covering the sacrifice layer; forming an electronic device on the sacrifice layer with the supporting layer in between; exposing at least a part of a side face of the sacrifice layer by removing a part of the supporting layer; forming a support body between the electronic device and the supporting layer, and a surface of the first substrate; removing the sacrifice layer; breaking the support body and transferring the electronic device onto a second substrate by bringing the electronic device into close contact with an adhesion layer provided on a surface of the second substrate; removing a fragment of the support body belonging to the electronic device; removing at least an exposed region in the adhesion layer not covered with the electronic device; and forming a fixing layer on a

Abstract: Activated resinous composition contains, on the basis of epoxy resin being solid at a room temperature of 100 parts by weight, carboxylic acid compound of 1 to 10 parts by weight, hardening agent of 1 to 30 parts by weight, a hardening reaction initiation temperature of said hardening agent being 150° C. or higher, and solvent of 10 to 300 parts by weight.

Abstract: A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies.

Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

Abstract: In a process for manufacturing a semiconductor device comprising heating a wiring board on which a chip and an uncured adhesive layer are laminated for curing the adhesive layer, the improvement includes performing a statically pressurizing step before the adhesive layer is cured, in which step the wiring board on which the chip and the uncured adhesive layer are laminated is subjected to a static pressure greater than atmospheric pressure by not less than 0.05 MPa. According to the process, voids are easily eliminated irrespective of the design of the wiring board, and the adhesive is prevented from curling up on the chip.

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.

Abstract: The present invention provides a heat-resistant pressure-sensitive adhesive tape for the production of a semiconductor device, which includes a base material layer having a glass transition temperature exceeding 180° C., and a pressure-sensitive adhesive layer having an elastic modulus at 180° C. of 1.0×105 Pa or more, which is formed on one side or both sides of the base material layer. The heat-resistant pressure-sensitive adhesive tape of the present invention can be used for temporarily fixing a chip in a production method of a substrateless semiconductor package which does not use a metal frame (for example, a production method of WLP).

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.

Abstract: The present invention provides a pressure-sensitive adhesive tape for resin encapsulation in production of a resin encapsulation type semiconductor device, which includes a base material layer which does not have a glass transition temperature in a temperature region of 260° C. or lower and a pressure-sensitive adhesive layer laminated on the base material layer, and a method for producing a resin encapsulation type semiconductor device using the pressure-sensitive adhesive tape. The pressure-sensitive adhesive tape according to the present invention highly prevents resin leakage even under severe conditions as in MAP-QFN production process, does not affect certainty of wire bonding and has excellent peelability after resin encapsulation.

Abstract: An object of the present invention is to provide an adhesive for electronic components that allows suppression of occurrence of voids and is prevented from wicking up to an upper surface of a semiconductor chip. Another object of the present invention is to provide a production method for a semiconductor chip mount using the adhesive for electronic components. The present invention is an adhesive for electronic components, including a curable compound, a curing agent, and an inorganic filler, wherein A1 and A2/A1 fall within a range surrounded by solid lines and a dashed line in FIG. 1 wherein a viscosity at 5 rpm measured at 25° C. using an E type viscometer is A1 (Pa·s) and a viscosity at 0.5 rpm measured at 25° C.

Abstract: Placement of an encapsulation material adhesion promoter onto a semiconductor device leadframe can be performed through the use of an offset printing apparatus such as a rotogravure printing apparatus or a tampoprint printing apparatus. This can provide accurate and low-cost placement of the adhesion promoter.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.

Abstract: Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the steps of pasting a film for forming a protective layer in which a support base, an adhesive layer, and a thermosetting resin layer are laminated, in that order, onto a bumped wafer in which a low dielectric material layer is formed, with the thermosetting resin layer serving as a pasting surface, and further, peeling the support base and the adhesive layer from the thermosetting resin layer, forming a protective layer by thermally curing the thermosetting resin layer, and dicing the bumped wafer and the protective layer together.

Abstract: A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.

Abstract: A method of manufacturing a semiconductor device, includes: placing a semiconductor element on an adhesive layer that is placed on a support body having a first through hole; placing a part in an area that includes a portion corresponding to the first through-hole, the portion being on the adhesive layer placed on the support body; forming a substrate on the adhesive layer by forming a resin layer on the adhesive layer, on which the semiconductor element and the part have been placed, the substrate including the semiconductor element, the part, and the resin layer; and detaching the substrate from the adhesive layer by pressing the part through the first through-hole.

Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.

Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

Abstract: A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.

Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.

Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the

Abstract: The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.

Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.

Abstract: A photosensitive adhesive capable of alkali development, the photosensitive adhesive exhibiting adhesion property for an adherend after it has been patterned by light exposure and development, the photosensitive adhesive being used in a method for producing a semiconductor device 100 comprising a step of patterning the photosensitive adhesive 1 provided on a circuit surface of a semiconductor chip 20 by light exposure and development; and a step of directly bonding another semiconductor chip 21 to the patterned photosensitive adhesive 1.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Abstract: A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads.

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An adhesive material is deposited over a portion of the semiconductor die and carrier to secure the semiconductor die to the carrier. The adhesive material is deposited over a side of the semiconductor die and over a surface of the carrier. The adhesive material can be deposited over a corner of the semiconductor die, or over a side of the semiconductor die, or around a perimeter of the semiconductor die. An encapsulant is deposited over the semiconductor die and carrier. The adhesive material reduces shifting of the semiconductor die with respect to the carrier during encapsulation. The adhesive material is cured and the carrier is removed. The adhesive material can also be removed. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die are singulated through the encapsulant and interconnect structure.

Abstract: A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.

Abstract: A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.

Abstract: A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.