Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

Abstract: The present disclosure provides a method for manufacturing the flexible display device. The method for manufacturing the flexible display device includes the following steps. First, a flexible substrate and a bonding structure are provided, in which the bonding structure is disposed on the flexible substrate. Subsequently, an anisotropic conductive film is provided on the bonding structure. Then, a driving circuit is provided on the anisotropic conductive film. Thereafter, the anisotropic conductive film is cured at a bonding temperature greater than or equal to 140° C. and less than or equal to 165° C.

Abstract: A display apparatus including a panel substrate including a TFT drive circuit for active matrix driving, a plurality of light emitting diodes, and an anisotropic conductive film electrically connecting the light emitting diodes to the panel substrate, in which the anisotropic conductive film includes an adhesive organic insulation material and conductive particles dispersed in the adhesive organic insulation material.

Abstract: Methods and apparatus are provided to improve the yield rate of LED packaging using LED flip chips. In one novel aspect, extended pads made of sintered silver are disposed on the cathode and the anode of the LED flip chip. The thickness of the extended pad is from about 25 ?m to about 200 ?m. In another embodiment, the LED flip chip further comprises a phosphor layer such that the LED flip chip emits white light. In another novel aspect, the LED flip chip with extended pads made of sintered silver is produced at the wafer level. The wafer level process involves applying sintering silver pastes to the cathode and the anode of each LED flip chip formed on the wafer and sintering the wafer at a temperature about 180° C. to about 240° C. for about two hours. The wafer is cut to individual LED flip chips with extended sintered silver pads.

Abstract: A microheater performs a self measurement of its own temperature. The microheater has an electrically resistive element which generates heat when a voltage has been applied across the resistive element. The resistive element has an electrical conductivity that is a function of its temperature. A measurement device is positioned within the microheater body and is configured to measure conductivity of the resistive element. An electronic processor, that may be incorporated into the microheater, controls brief interruption of the heating voltage and application of a lower voltage for measuring conductivity. The lower voltage is insufficient to increase the heat output of the microheater, and is applied for too short of a period to allow excessive cooling of the microheater. A microprocessor receives and processes the data obtained from measuring conductivity.

Abstract: A semiconductor device includes a surface metal formed on a substrate, a first protective film formed on the surface metal, a second protective film having a first portion provided on the first protective film and a second portion continuing to the first portion and provided on the surface metal and being transparent to light, and a metal film having a main body portion provided on the surface metal and a run-on portion continuing to the main body portion and running onto the first protective film, wherein the main body portion is thicker than the first protective film, the first portion is thicker than the run-on portion, and the second portion is thicker than the main body portion.

Abstract: A molding die device is provided for bringing a resin sheet into close contact with a pair of dies by vacuum suction from a cavity surface to perform molding. An outer frame portion is formed integrally with an outer peripheral portion of the respective dies arranged to face each other. Moreover, one of the dies has a recessed portion formed at the position of the one of the dies facing the outer frame portion of the other die and configured so that the outer frame portion of the one of the dies can be housed in the recessed portion. The outer frame portion is formed to protrude most in each die. Upon molding, the dies are clamped together after vacuum suction has been performed with the resin sheet being arranged in contact with the outer frame portions.

Abstract: A card exhibiting enhanced detection is provided. A plurality of detector shapes that may be associated with a detection system increases detection effectiveness, while reducing adverse effects of detection systems that may be operating within a electromagnetic field environment.

Abstract: According to a first aspect of the present disclosure, an electronic device is provided which comprises: a substrate; an integrated circuit; a layer of glue between the substrate and the integrated circuit; a set of driving electrodes coupled to the glue and to the integrated circuit; a receiving electrode coupled to the glue and to the integrated circuit; a counter electrode coupled to the glue and to the substrate; wherein the glue comprises conductive particles which electrically connect the receiving electrode, the counter electrode and at least a part of the set of driving electrodes, such that, if drive currents are provided to said set of driving electrodes, at least a part of the drive currents flows to the receiving electrode through the conductive particles and the counter electrode. According to a second aspect of the present disclosure, a corresponding method of manufacturing an electronic device is conceived.

Abstract: A lead frame used to produce a chip package includes a first lead frame section and a second lead frame section connected to one another by a bar, wherein the bar includes a first longitudinal section, a second longitudinal section and a third longitudinal section, the first longitudinal section adjoins the first lead frame section and the third longitudinal section adjoins the second lead frame section, the first longitudinal section and the third longitudinal section are oriented parallel to one another, the first longitudinal section and the second longitudinal section form an angle not equal to 180° and not equal to 90°, and the lead frame is planar.

Abstract: A MEMS device includes a first substrate provided with a plurality of first electrode terminals and a second substrate composed of a crystalline substrate and provided with a plurality of second electrode terminals respectively corresponding to the first electrode terminals. The first electrode terminals and the second electrode terminals are electrically bonded one-to-one. Protrusions are formed at positions corresponding to the first electrode terminals on a mounting face of the second substrate opposing the first substrate. The second electrode terminals include the protrusions and conductive material covering the protrusions.

Abstract: A dielectric material suitable for use in an electronic component includes bismuth ferrite, strontium titanate and an additive. The additive comprises barium titanate. The barium titanate reduces the temperature capacitance change of the dielectric material and allows for increased working voltages. The material is useful for the construction of capacitors, and particularly capacitors intended for use at high temperatures. Also provided are a capacitor including the dielectric material, methods of manufacturing the dielectric material and the capacitor, and the use of an additive to improve the lifetime and/or reduce the dissipation factor of a capacitor.

Abstract: A wafer is divided along a plurality of crossing division lines to obtain a plurality of individual devices. The division lines are formed on the front side of the wafer to define a plurality of separate device regions. An adhesive film is applied to the back side of the wafer and the other side of the adhesive film is attached to a dicing tape composed of a base sheet and an ultraviolet curable adhesive layer formed on the base sheet. The adhesive film is attached to the ultraviolet curable adhesive layer of the dicing tape. Ultraviolet light is applied to the dicing tape to thereby cure the adhesive layer. A rotating cutting blade cuts the wafer together with the adhesive film along the division lines, dividing the wafer into the individual devices. The cutting blade is positioned so that its cutting edge cuts into the cured adhesive layer.

Abstract: In accordance with certain embodiments, phosphor chips are formed and subsequently attached to light-emitting elements.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.

Abstract: An apparatus for providing localized heating as well as protection for a vibrating MEMS device. A cap over a MEMS gyroscope includes an embedded temperature sensor and a heater. The temperature sensor is a trace made of a material with a known temperature/resistance coefficient, which loops back along itself to reduce electromagnetic interference. The heater is a resistive metal trace which also loops back along itself. The temperature sensor and the heater provide localized temperature stabilization for the MEMS gyroscope to reduce temperature drift in the MEMS gyroscope.

Abstract: A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.

Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Abstract: An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.

Abstract: Provided are a metal payment card and a method of manufacturing the same. The metal payment card of the present disclosure has a main body made from at least one of a liquid metal alloy, aluminum alloy and copper alloy. The main body has a tangible pattern region.

Abstract: Provided are a stretchable electronic device and a method of manufacturing the same. The manufacturing method includes forming coil interconnection on a first substrate, forming a first stretchable insulating layer that covers the coil interconnection, forming a second substrate on the first stretchable insulating layer, separating the first substrate from the coiling interconnection and the first stretchable insulating layer, and forming a transistor on the coil interconnection.

Abstract: Substrates and semiconductor chips are provided. The substrate or the semiconductor chip includes a body and a substantially pillar-shaped bump disposed on a first surface of the body. The pillar-shaped bump has a hole penetrating a portion thereof. Related semiconductor packages are also provided. Further, related methods are provided.

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract: Methods of fabricating integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated said die except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

Abstract: Articles containing a matrix material and plurality of copper nanoparticles in the matrix material that have been at least partially fused together are described. The copper nanoparticles are less than about 20 nm in size. Copper nanoparticles of this size become fused together at temperatures and pressures that are much lower than that of bulk copper. In general, the fusion temperatures decrease with increasing applied pressure and lowering of the size of the copper nanoparticles. The size of the copper nanoparticles can be varied by adjusting reaction conditions including, for example, surfactant systems, addition rates, and temperatures. Copper nanoparticles that have been at least partially fused together can form a thermally conductive percolation pathway in the matrix material.

Abstract: Semiconductor die are assembled on a substrate by providing the semiconductor die, substrate, and an elastically deformable foil fixture preformed with one or more sunken regions having sidewalls and a bottom, and placing the semiconductor die in the one or more sunken regions so that the foil fixture is populated with a first side of the semiconductor die facing the bottom of the one or more sunken regions and a second opposing side of the semiconductor die facing away from the bottom of the one or more sunken regions. The substrate is placed adjacent the second side of the semiconductor die with a joining material interposed between the substrate and the semiconductor die. The substrate and the populated foil fixture are pressed together at an elevated temperature and pressure via first and second pressing tool members so that the substrate is attached to the second side of the semiconductor die via the joining material.

Abstract: Apparatus and methods provide for utilizing continuous curved composite stringers to control the loads and corresponding moments within curved regions of an aircraft or other vehicle without delamination or other interlamina failures. According to embodiments described herein, any number of tapered height curved composite stringers may be coupled to continuous skin components to create a curved continuous panel. The tapered height curved composite stringers may have webs that taper to a reduced height within curved regions and corresponding base flanges that widen during web tapering. Reinforcement fittings may be coupled to the base flanges in the curved regions for further strengthening and to provide for the attachment of supplemental panels to the stringers.

Abstract: Sub-micron precision alignment between two microelectronic components can be achieved by applying energy to incite an exothermic reaction in alternating thin film reactive layers between the two microelectronic components. Such a reaction rapidly distributes localized heat to melt a solder layer and form a joint without significant shifting of components.

Abstract: Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer hav

Abstract: A method of manufacturing a micro structure, includes the steps of: preparing separate first and second substrates, the first substrate having a first surface on which a first structural body having a first height and a second structural body having a second height greater than the first height of the first structural body are arranged, the second substrate having a second surface; then placing the first and second substrates to cause the first and second surfaces to face each other across the first and second structural bodies; and then bonding the first and second substrates to each other while compressing the second structural body in a height direction thereof between the first and second surfaces to cause the second structural body to have a height defined by the first structural body.

Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.

Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Abstract: A method for manufacturing a chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.

Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30?) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30?) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30?) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).

Abstract: A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier.

Abstract: A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.

Abstract: A method for producing a semiconductor module includes providing an adhesion carrier and a plurality of circuit carriers. The adhesion carrier has an adhesive upper side and a lower side opposite the adhesive upper side. Each of the circuit carriers includes a ceramic carrier and an upper conductor layer applied to the ceramic carrier, and a circuit carrier lower side. By placing the circuit carriers onto the adhesive upper side, the circuit carrier lower side of the circuit carriers contacts and adheres to the adhesive upper side, so that a quasi-panel is formed, in which the circuit carriers are processed while preserving the quasi-panel and can then be removed from the adhesive upper side.

Abstract: A semiconductor device includes: a semiconductor chip having a main face which has a pair of long sides parallel to each other and a pair of short sides orthogonal to the pair of long sides; first bumps arrayed in a first bump placement region of the semiconductor chip, the first bump placement region being positioned along one of the pair of long sides; second bumps arrayed in a second bump placement region of the semiconductor chip, the second bump placement region being positioned along the other of the pair of long sides; first power lines disposed in a region between the first bump placement region and the second bump placement region, the first power lines extending in a direction parallel to the pair of long sides; and third bumps integrated on the semiconductor chip. Each of the third bumps provides short-circuiting of the first power lines.

Abstract: A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). The lid (24) includes a cavity (25) in which dies (38) mounted to the base (22) are located. A gap (70) is formed without the adhesive (64) at the section (68) between the base (22) and the lid (24). The structure vents from the gap (70) as air inside the cavity (25) expands during heat curing (72). Following heat curing (72), another adhesive (80) is dispensed in the section (68) to close the gap (70) and seal the cavity (25).

Abstract: According to the present invention, a resin composition having superior workability is provided. The paste-like resin composition of the present invention adheres a semiconductor element and a base material, and contains (A) a thermosetting resin and (B) metal particles. d95 in the volume-based particle size distribution of the metal particles as determined with a flow-type particle image analyzer is 10 ?m or less. In other words, the volume ratio of metal particles having a particle diameter that exceeds 10 ?m is less than 5%. Here, d95 indicates the particle diameter at which the cumulative volume ratio thereof is 95%.

Abstract: A method for bonding wafers includes forming a first bonding part on a surface of a first wafer by stacking a diffusion preventing layer formed of a material having low wettability with AuSn above the first wafer and forming a bonding layer on a surface of the diffusion preventing layer such that the bonding layer stays back of an edge of the diffusion preventing layer, forming a second bonding part on a surface of a second wafer, and bonding the first bonding part and the second bonding part by eutectic bonding with an AuSn solder under a condition that the first wafer and the second wafer are opposed to each other.

Abstract: The invention provides a wafer-bonded semiconductor device wherein warpage generated when wafers are bonded is reduced at a low cost ad through a simple process. In a method for manufacturing a wafer-bonded semiconductor device by bonding a first wafer substrate and a second wafer substrate together, the method of the invention includes a first step of forming in advance bonding members having a bonding function when heated on the wafer-bonded surface sides of the first wafer substrate and the second wafer substrate, respectively; a second step of supplying flux paste containing two or more kinds of powdery materials having reactivity to the surfaces of the bonding members formed in the first step; and a third step of causing excitation to have the flux paste supplied in the second step start reacting.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Abstract: An LED includes a compound semiconductor structure having first and second compound layers and an active layer, first and second electrode layers atop the second compound semiconductor layer and connected to respective compound layers. An insulating layer is coated in regions other than where the first and second electrode layers are located. A conducting adhesive layer is formed atop the non-conductive substrate, connecting the same to the first electrode layer and insulating layer. Formed on one side surface of the non-conductive substrate and adhesive layer is a first electrode connection layer connected to the conducting adhesive layer. A second electrode connection layer formed on another side surface is connected to the second electrode layer. By forming connection layers on respective side surfaces of the light-emitting device, manufacturing costs can be reduced.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.