Majority Signal Carrier (e.g., Buried Or Bulk Channel, Peristaltic, Etc.) Patents (Class 438/146)
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Patent number: 9554495Abstract: An electro-optic display is produced using a sub-assembly comprising a front sheet, an electro-optic medium; and an adhesive layer. An aperture is formed through the adhesive layer where the adhesive layer is not covered by the electro-optic medium, and the sub-assembly is adhered to a backplane having a co-operating member with the aperture engaged with a co-operating member, thus locating the sub-assembly relative to the backplane. In another form of electro-optic display, a chip extends through an aperture in the electro-optic medium and adhesive layer. In a third form, the aforementioned sub-assembly is secured to a backplane and then a cut is made through both backplane and sub-assembly to provide an aligned edge.Type: GrantFiled: December 24, 2013Date of Patent: January 24, 2017Assignees: E Ink Corporation, Samsung Electronics Co., Ltd.Inventors: Guy M. Danner, Valerie C. Northrop, Jonathan D. Albert, Holly G. Gates, Erik van Veenendaal, Fredericus J. Touwslager
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Patent number: 8913252Abstract: A computing device is electronically connected to a measurement machine and a controller. The controller is connected to a sensor installed on the measurement machine. The computing device receives spectral signal data sent from the controller and generates an intensity distribution diagram according to the spectral signal data. Furthermore, the computing device sends control commands to the measurement machine, to adjust a position of the sensor on the measurement machine according to variation of a peak value of a wave in the intensity distribution diagram.Type: GrantFiled: December 18, 2013Date of Patent: December 16, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Chih-Kuang Chang, Li Jiang, Zhong-Kui Yuan, Wei-Wen Wu, Xiao-Guang Xue, Jian-Hua Liu
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Patent number: 8741700Abstract: Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element.Type: GrantFiled: August 20, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Fei Liu, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8642430Abstract: Processes for preparing a stressed semiconductor wafer and processes for preparing devices including a stressed semiconductor wafer are provided herein. An exemplary process for preparing a stressed semiconductor wafer includes providing a semiconductor wafer of a first material having a first crystalline lattice constant. A stressed crystalline layer of a second material having a different lattice constant from the first material is pseudomorphically formed on a surface of the semiconductor wafer. A first via is etched through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer. The first via in the semiconductor wafer is filled with a first filler material to impede dissipation of stress in the semiconductor wafer.Type: GrantFiled: April 9, 2012Date of Patent: February 4, 2014Assignee: Globalfoundries, Inc.Inventors: Stefan Flachowsky, Thilo Scheiper
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Patent number: 8551810Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.Type: GrantFiled: March 25, 2011Date of Patent: October 8, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8461630Abstract: A conductive film to be a gate electrode, a first insulating film to be a gate insulating film, a semiconductor film in which a channel region is formed, and a second insulating film to be a channel protective film are successively formed. With the use of a resist mask formed by performing light exposure with the use of a photomask which is a multi-tone mask and development, i) in a region without the resist mask, the second insulating film, the semiconductor film, the first insulating film, and the conductive film are successively etched, ii) the resist mask is made to recede by ashing or the like and only the region of the resist mask with small thickness is removed, so that part of the second insulating film is exposed, and iii) the exposed part of the second insulating film is etched, so that a pair of opening portions is formed.Type: GrantFiled: November 18, 2011Date of Patent: June 11, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Kosei Noda
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Patent number: 8383448Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.Type: GrantFiled: January 5, 2012Date of Patent: February 26, 2013Assignee: United Microelectronics Corp.Inventor: Ching-Hung Kao
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Patent number: 8247294Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.Type: GrantFiled: November 15, 2010Date of Patent: August 21, 2012Assignee: NEC CorporationInventors: Kiyoshi Takeuchi, Katsuhiko Tanaka
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Patent number: 8193031Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.Type: GrantFiled: November 17, 2010Date of Patent: June 5, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Miyuki Hosoba, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
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Patent number: 8119474Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.Type: GrantFiled: January 15, 2010Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Andres Bryant, Edward J. Nowak, Richard Q. Williams
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Patent number: 8105924Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.Type: GrantFiled: January 21, 2010Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
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Patent number: 7977200Abstract: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.Type: GrantFiled: March 12, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: William F. Clark, Jr., Stephen E. Luce
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Patent number: 7807514Abstract: A method of forming a charge-coupled device including the steps of forming well or substrate of a first conductivity type; a buried channel of a second conductivity type; a plurality of first gate electrodes; partially coating the first gate electrodes with a mask substantially aligned to an edge of the first gate electrodes; implanting ions of the first conductivity type of sufficient energy to penetrate the first gates and into the buried channel; and a plurality of second gate electrodes covering regions each over the buried channel between the first gate electrodes.Type: GrantFiled: April 26, 2006Date of Patent: October 5, 2010Assignee: Eastman Kodak CompanyInventors: Christopher Parks, John P. McCarten, Joseph R. Summa
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Patent number: 7723145Abstract: A solid-state imaging device includes a semiconductor substrate including: a plurality of light-receptive portions that are arranged one-dimensionally or two-dimensionally; a vertical transfer portion that transfers signal electric charge read out from the light-receptive portions in a vertical direction; a horizontal transfer portion that transfers the signal electric charge transferred by the vertical transfer portion in a horizontal direction; a barrier region adjacent to the horizontal transfer portion, the barrier region letting only surplus electric charge of the horizontal transfer portion pass therethough; a drain region adjacent to the barrier region, into which the surplus electric charge passing through the barrier region is discharged; and an insulation film adjacent to the drain region. A portion of the drain region is located beneath the insulation film.Type: GrantFiled: November 20, 2008Date of Patent: May 25, 2010Assignee: Panasonic CorporationInventor: Toshihiro Kuriyama
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Patent number: 7691734Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.Type: GrantFiled: March 1, 2007Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
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Patent number: 7544552Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.Type: GrantFiled: March 23, 2006Date of Patent: June 9, 2009Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
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Patent number: 7314801Abstract: A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a method of forming the same.Type: GrantFiled: December 20, 2005Date of Patent: January 1, 2008Assignee: Palo Alto Research Center IncorporatedInventors: Peter Kiesel, Oliver Schmidt, Arnd Willy Walter Geis, Noble Marshall Johnson
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Patent number: 7052939Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).Type: GrantFiled: November 26, 2002Date of Patent: May 30, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Wen Ling M. Huang, Sushil Bharatan, Carl Kyono, David J. Monk, Kun-Hin To, Pamela J. Welch
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Patent number: 6927091Abstract: Disclosed is a method for fabricating a solid-state imaging device including a semiconductor substrate of a first conductivity type, a plurality of light-receiving sections provided at a distance in the surface region of the semiconductor substrate, and channel stop regions of a second conductivity type provided between the adjacent light-receiving sections in the surface region and in the internal region of the semiconductor substrate. The method includes the steps of forming a first photoresist layer having openings corresponding to positions at which the channel stop regions are formed; ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a first energy through the first photoresist layer as a mask; forming a second photoresist layer having openings; and ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a second energy through the second photoresist layer as a mask.Type: GrantFiled: August 19, 2002Date of Patent: August 9, 2005Assignee: Sony CorporationInventor: Kouichi Harada
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Publication number: 20040259293Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.Type: ApplicationFiled: February 27, 2003Publication date: December 23, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Tooru Yamada
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Publication number: 20040180476Abstract: A backplane for use in an electro-optic display comprises a patterned metal foil having a plurality of apertures extending therethrough, coated on at least side with an insulating polymeric material and having a plurality of thin film electronic devices provided on the insulating polymeric material.Type: ApplicationFiled: November 25, 2003Publication date: September 16, 2004Applicant: E INK CORPORATIONInventors: Peter T. Kazlas, Joanna F. Au, Yu Chen, Nathan R. Kane, David John Cole
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Patent number: 6780686Abstract: The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region is greater than the first dopant concentration level in the bulk substrate, the first doped region being substantially aligned with the gate electrode.Type: GrantFiled: March 21, 2002Date of Patent: August 24, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Andy C. Wei, Derick J. Wristers, Mark B. Fuselier
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Patent number: 6713323Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.Type: GrantFiled: January 29, 2002Date of Patent: March 30, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Takashi Hamada, Satoshi Murakami
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Patent number: 6649454Abstract: A process for forming a portion of a charge coupled device (CCD) is described. More particularly, wells (105) are formed self-aligned under gate stacks (132, 134). By forming wells (105) self-aligned to respective first and second gates (107, 207) of gate stacks (132, 134), potential for misalignment is reduced. First gates (107) of gate stacks (132) may be coupled together, and second gates (207) of gate stacks (134) may be coupled together, and these first and second gates (107, 207) may be coupled to respective signal sources (23, 24) to form a two-phase CCD.Type: GrantFiled: November 10, 2000Date of Patent: November 18, 2003Assignee: Sarnoff CorporationInventors: Pradyumna Kumar Swain, Vipulkumar Kantilal Patel
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Patent number: 6573138Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: July 8, 1999Date of Patent: June 3, 2003Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6555421Abstract: A method and apparatus for manufacturing a semiconductor device can achieve the formation of thin films in a uniform thickness on a substrate. The method and apparatus includes a film-forming process in which film-forming gases 14, 15 are caused to flow over a surface of a substrate 11 substantially in parallel therewith to form thin films on the substrate surface. The film-forming process includes an initial film-forming step for forming a first thin film on the surface of the substrate 11 under a first film-forming conditions and a main film-forming step for forming, on the first thin film acting as a backing layer, a second thin film of a thickness greater than that of the first thin film under a second film-forming condition which differs from the first film-forming condition.Type: GrantFiled: January 12, 2001Date of Patent: April 29, 2003Assignee: Hitachi Kokusai Electric Inc.Inventors: Naoko Matsuyama, Sinya Sasaki
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Patent number: 6432763Abstract: For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is formed on the gate dielectric. An amorphous semiconductor structure, which may be comprised of amorphous silicon for example, is formed on the doped gate electrode. A hardmask structure comprised of a hardmask dielectric material is formed on the amorphous semiconductor structure. The gate dielectric, the doped gate electrode, the amorphous semiconductor structure, and the hardmask structure form a gate stack. Liner dielectric structures are formed on sidewalls of the gate stack. A dopant is implanted into exposed regions of the semiconductor substrate after forming the liner dielectric structures on the sidewalls of the gate stack.Type: GrantFiled: March 15, 2001Date of Patent: August 13, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6380005Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N−− semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N−− semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N−− semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.Type: GrantFiled: April 7, 2000Date of Patent: April 30, 2002Assignee: NEC CorporationInventor: Yasutaka Nakashiba
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Publication number: 20010035538Abstract: A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.Type: ApplicationFiled: December 1, 1999Publication date: November 1, 2001Inventors: YUKIYA KAWAKAMI, SHIGERU TOHYAMA
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Publication number: 20010010942Abstract: A solid state image sensor device and a method of fabricating the same are disclosed in the present invention. A solid state image sensor device includes a semiconductor substrate, a well region in the semiconductor substrate, a horizontal charge transmission region in the well region, a plurality of insulating layers in the horizontal charge transmission region, a gate insulating layer on the entire surface including the insulating layers, a plurality of first polygates on the gate insulating layer, the first polygates being separated from each other and overlapping a portion of each insulating layer, a plurality of impurity regions in the horizontal charge transmission region at both sides of each first polygate, an interlayer insulating layer on the entire surface including the first polygates, and a plurality of second polygates on the interlayer insulating layer and overlapped with a portion of each first polygate.Type: ApplicationFiled: March 16, 2001Publication date: August 2, 2001Applicant: LG Semicon Co., Ltd.Inventor: Sun Choi
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Publication number: 20010004116Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.Type: ApplicationFiled: December 8, 2000Publication date: June 21, 2001Applicant: NEC CorporationInventor: Shiro Tsunai
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Patent number: 6210990Abstract: Method for fabricating a solid state image sensor, which can improve a charge transfer efficiency of an end terminal, including the steps of (1) providing a first conduction type substrate having a second conduction type well and a BCCD formed therein for an end terminal, (2) continuously increasing impurity concentrations in a region of the substrate in which a floating diffusion region is to be formed and in a portion of an area of other substrate in which the regions are are to be formed for improving a horizontal charge transfer efficiency, and (3) forming transfer gates, an output gate, and reset gate on the substrate, and the floating diffusion region and a reset drain region in the BCCD, respectively.Type: GrantFiled: July 9, 1999Date of Patent: April 3, 2001Assignee: LG Semicon Co., Ltd.Inventor: Kyoung Kuk Kwon
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Patent number: 6194748Abstract: A method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).Type: GrantFiled: May 3, 1999Date of Patent: February 27, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6133063Abstract: In a process for producing a pin layer sequence on a perovskite of the type ABO.sub.3 which has AO layers, AO layers are converted such that a p-conductive B-oxide rich layer and, disposed therebetween an ABO.sub.3 layer with intrinsic conductivity are formed. Also, a perovskite of the type ABO.sub.3 with a layer sequence on the surface which includes an AO-enriched (ABO.sub.3)-layer, a B-oxide rich layer and disposed therebetween an ABO.sub.3 layer and an electronic building element comprising such a perovskite.Type: GrantFiled: October 22, 1998Date of Patent: October 17, 2000Assignee: Forschungszentrum Julich GmbHInventors: Wolfgang Speier, Krzysztof Szot
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Patent number: 6107124Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.Type: GrantFiled: November 23, 1999Date of Patent: August 22, 2000Assignee: LG Semicon Co., Ltd.Inventors: Yong Park, Do Hyung Kim, Sang Ho Moon
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Patent number: 6054341Abstract: A charge-coupled device includes a first P-type well formed in an N-type semiconductor substrate, a second P-type well formed repeatedly the first P-type well region, a charge-transfer region (BCCD) formed within the second P-type well region, an N-type photodiode region (PDN) formed in the upper portion of the first P-type well so as to be isolated from the charge-transfer region, a first high concentration P-type photodiode region (first PDP.sup.+ region) formed in the upper surface of the N-type photodiode region excluding the charge-transfer region and serving as a charge-isolating layer, first and second poly-gates formed repeatedly on the charge-transfer region, and a second high concentration self aligned P-type photodiode region (second PDP.sup.+ region) formed in the surface of the first high concentration P-type photodiode region. The charge-isolating region is thin to extend the potential pocket of each light-conversion PDN region.Type: GrantFiled: February 3, 1998Date of Patent: April 25, 2000Assignee: LG Semicon Co., LtdInventor: Yong Gwan Kim
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Patent number: 5981309Abstract: A method for fabricating a CCD image sensor includes the steps of forming a P type well in a surface of a semiconductor substrate, forming a buried CCD (BCCD) in a surface of the P type well, forming an offset gate and a reset gate on the BCCD at a predetermined interval, forming a floating diffusion region in the BCCD between the offset gate and the reset gate, forming a mask layer on an entire surface of the semiconductor substrate to form a contact hole in the floating diffusion region, forming a metal layer on the entire surface of the semiconductor substrate including the contact hole, and selectively removing the metal layer on the mask layer together with the mask layer to form a floating gate in the contact hole.Type: GrantFiled: September 22, 1997Date of Patent: November 9, 1999Assignee: LG Semicon Co., Ltd.Inventors: Hang Kyoo Kim, Yong Park, Sun Choi
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Patent number: 5972733Abstract: A method for making a virtual phase charge coupled device includes: forming a semiconductor region 24; forming a gate insulator layer 26 over the semiconductor region 24; forming a semiconductor layer over the gate insulator layer 26; forming first, second, and third openings in the semiconductor layer; implanting antiblooming barrier implants 36 in the semiconductor region 24 through the first opening; implanting virtual barrier implants 42 in the semiconductor region through the second opening; implanting clocked barrier implants 46 in the semiconductor region 24 through the third opening; forming semiconductor fillings in the first, second, and third openings; etching the semiconductor layer and semiconductor fillings to form clocked gates 28 and 30 and an antiblooming gate 32; implanting an antiblooming drain 48 aligned to the antiblooming gate 32; and implanting virtual gates 56, 58, and 60 aligned to the clocked gates 28 and 30 and the antiblooming gate 32.Type: GrantFiled: February 17, 1998Date of Patent: October 26, 1999Assignee: Texas Instruments IncorporatedInventor: Jaroslav Hynecek
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Patent number: 5858812Abstract: A solid-state image sensor has a photodiode region, a vertical CCD register for transferring a charge received at the photodiode region, a read-out gate region for reading the charge out to the vertical CCD register, and an element isolation region for isolating the photodiode region and the vertical CCD register. Ion-implantation is carried out first for the element isolation region and, thereafter, the photodiode region and the vertical CCD register are formed. The element isolation region is in a two layer configuration having a P.sup.+ -type region and a P-type region, and the P-type region is formed simultaneously with other regions including the read-out gate region. When the P-type region for the element isolation region is formed by ion-implantation before the formation of the photodiode region and the vertical CCD register, the fine patterning of the resist mask becomes unnecessary.Type: GrantFiled: February 20, 1997Date of Patent: January 12, 1999Assignee: NEC CorporationInventor: Masayuki Furumiya
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Patent number: 5788763Abstract: In a heat history initializing step, a heat treatment in performed in an atmosphere including at least one of hydrogen, helium, and argon while the temperature is increased in a range of 700.degree. C. to 1,000.degree. C. at a rate of 15.degree.-1,000.degree. C./min. In a controlled nuclei growing step, a heat treatment is performed in the above atmosphere while the temperature is kept constant in a range of 850.degree. C. to 980.degree. C. for 0.5-60 minutes.Type: GrantFiled: March 7, 1996Date of Patent: August 4, 1998Assignee: Toshiba Ceramics Co., Ltd.Inventors: Kenro Hayashi, Ryuji Takeda, Katsuhiro Chaki, Ping Xin, Jun Yoshikawa, Hiroyuki Saito
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Patent number: 5773324Abstract: A bidirectional horizontal charge transfer device and method includes a charge transfer area formed within a substrate, a plurality of first, second, third and fourth poly gates formed over the charge transfer area, an insulating layer formed between the first, second, third and fourth poly gates, a first clock signal applied to the first and second poly gates, a second clock signal applied to the third and fourth poly gates, and a biasing circuit for selectively applying a bias signal to the first and second clock signals so as to selectively change a charge transfer direction.Type: GrantFiled: July 30, 1996Date of Patent: June 30, 1998Assignee: LG Semicon Co., Ltd.Inventors: Jee Sung Yoon, Il Nam Hwang