Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

Abstract: The purpose of the present invention is to prevent forming of soot like black substance on the back of the TFT substrate of resin during laser ablation to separate the glass substrate from the TFT substrate. The present invention takes the following structure to counter measure the above problem. A display device having pixels formed on a first surface of the resin substrate including: a first layer, formed from nitride, being formed on a second surface of the resin substrate, the second surface being an opposite surface to the first surface, in which a second layer, which is a separation layer, is formed on the first layer.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

Abstract: Example displays having transparent areas for cameras are disclosed. An example display has a first source line including a first portion composed of a first material and a second portion composed of a second material different than the first material. A first gate line includes a first portion composed of a third material and a second portion composed of a fourth material, the fourth material being different than the third material. A second gate line includes a first portion composed of the third material and a second portion composed of the fourth material. The first portion of the source line, the first portion of the first gate line, and the first portion of the second gate line define a non-transparent area of the display. The second portion of the source line, the second portion of the first gate line, and second portion of the second gate line define a transparent area of a display.

Abstract: A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.

Abstract: A multi-component coating composition for a surface of a chamber component comprising at least one first film layer of a yttrium oxide coated onto the surface of the chamber component using an atomic layer deposition process and at least one second film layer of zirconium oxide coated onto the surface of the chamber component using an atomic layer deposition process, wherein the multi-component coating comprises YZrxOy.

Abstract: A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N?3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion.

Abstract: An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

Abstract: A method of processing a workpiece includes: forming a ruthenium film on the workpiece and disposing a mask on the ruthenium film; etching the ruthenium film through a plasma processing; forming a protective film on the workpiece through an atomic layer deposition method, the protective film including a first region extending along a side wall surface of the mask and a second region extending over the ruthenium film; and etching the protective film so as to remove the second region while leaving the first region. The etching the ruthenium film includes a first step of etching the ruthenium film through a plasma processing using an oxygen-containing gas, and a second step of etching the ruthenium film through a plasma processing using a chlorine-containing gas. The first step and the second step are alternately performed.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin on a substrate. A dummy gate structure is formed crossing the semiconductor fin. The dummy gate structure is replaced with a metal gate structure. An epitaxial structure is formed in the semiconductor fin after replacing the dummy gate structure with the metal gate structure.

Abstract: A micro-LED transfer method, manufacturing method and display device are provided. The micro-LED transfer method comprises: bonding the micro-LED array on a first substrate onto a receiving substrate through micro-bumps, wherein the first substrate is laser transparent; applying underfill into a gap between the first substrate and the receiving substrate; irradiating laser onto the micro-LED array from a side of the first substrate to lift-off the micro-LED array from the first substrate; and removing the underfill.

Abstract: Nanoelectromechanical systems (NEMS) devices/switches and methods for implementing and fabricating the same with conducting contacts are provided. A nanoelectromechanical system (NEMS) switch can include a substrate; a source cantilever formed over the substrate and configured to move relative to the substrate; a drain electrode and at least one gate electrode formed over the substrate; wherein the source cantilever, drain and gate electrodes comprises a metal layer affixed to a support layer, at least a portion of the metal layer at the contact area extending past the support layer; and an interlayer sandwiched between the support layer and substrate.

Abstract: A laser soldering device for laser soldering an electric circuit of a heating portion of an electronic cigarette, the soldering device including a head having an emitting area where a laser beam is emitted and a feeding device to feed a heating portion of an electronic cigarette along a feed path, where the heating portion faces the head at the emitting area. A movement device is operatively connected to the head to move the head between first and second points of the electric circuit such that the laser beam is perpendicular to the respective surface to be soldered at the first and second points to form first and second connections, respectively. The head generates two distinct pulses of the laser beam at the first and second points.

Abstract: An electrical stimulation and monitoring device that includes multiple signal paths that are connected in parallel with each other, and each containing a stimulation or sensing electrode, a DC-blocking capacitor and a stimulation or sensing channel. A semiconductor substrate provided for hosting the DC-blocking capacitors is connected electrically to a DC voltage source through a substrate holding capacitor. Such substrate holding capacitor reduces a blanking time between stimulation and sensing periods, and also reduces cross-couplings between different ones of the signal paths while all the DC-blocking capacitors are provided on one and same semiconductor substrate.

Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating portion. The first semiconductor region includes first to third partial regions. The first partial region is provided between the first electrode and the second electrode. The second partial region is provided between the first and third electrodes. The second semiconductor region includes fourth to sixth partial regions. The fourth partial region is provided between the first partial region and the second electrode. The fifth partial region is provided between the third semiconductor region and at least a portion of the second partial region. The sixth partial region is provided between the third partial region and the third semiconductor region. The fourth semiconductor region is provided between the first and fourth partial regions. The first insulating portion is provided between the second partial region and the third electrode.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: Disclosed herein is a rare-earth oxide coating on a surface of an article with one or more interruption layers to control crystal growth and methods of its formation. The coating may be deposited by atomic layer deposition and/or by chemical vapor deposition. The rare-earth oxides in the coatings disclosed herein may have an atomic crystalline phase that is different from the atomic crystalline phase or the amorphous phase of the one or more interruption layers.

Abstract: A method may include providing a transistor structure on a substrate, where the transistor structure includes a semiconductor fin, a source/drain contact forming electrical contact with the semiconductor fin, and a gate conductor, disposed over the semiconductor fin, wherein the source drain contact and gate conductor are disposed in a trench. The method may further include directing angled ions to the trench, wherein the source/drain contact assumes a tapered shape.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.

Abstract: Method for fabricating at least one FET transistor (100a, 100b) comprising: fabrication of at least one first semiconducting portion (114) that will form a channel of the FET transistor, fabrication of second semiconducting portions (122, 124, 126) that will be used to form source and drain regions, such that the first semiconducting portion is located between first ends of the second semiconducting portions and such that second ends of the second semiconducting portions opposite the first ends, are in contact with bearing surfaces, and comprising at least one semiconducting material for which the crystalline structure or the atomic organisation, can be modified when a heat treatment is applied to it; heat treatment generating a modification to the crystalline structure of the semiconducting material of the second semiconducting portions and creating a strain (128) in the first semiconducting portion.

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.

Abstract: A display device includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels includes a transistor and a pixel electrode arranged above the transistor through a first protective film and a second protective film. Among the plurality of pixels, the pixel electrodes of two pixels adjacent in a column direction are connected to corresponding source electrodes of the two pixels through second and third contact holes respectively. The second and third contact holes are formed in the first protective film within a first contact hole that is formed in the second protective film.

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

Abstract: A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate. A method of fabricating the semiconductor structure includes fabricating the optoelectronic device in a device layer thin-film of SiC on a silicon wafer of a first diameter, transferring the device layer thin-film of SiC from the silicon wafer, and permanently bonding the device layer thin-film to a SiC surrogate substrate of a second diameter.

Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

Abstract: Methods of vapor deposition include multiple vapor sources. A vapor deposition method includes delivering pulses of a vapor containing a first source chemical to a reaction space from at least two separate source vessels simultaneously. The pulses can contain a substantially consistent concentration of the first source chemical. The method can include purging the reaction space of an excess of the first source chemical after the delivering, and delivering pulses of a vapor containing a second source chemical to the reaction space from at least two separate source vessels simultaneously after the purging.

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.

Abstract: Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or using of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract: Terahertz external modulator based on high electron mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

Abstract: The present invention relates to organic semiconductor compositions and organic semiconductor layers and devices comprising such organic semiconductor compositions. The invention is also concerned with methods of preparing such organic semiconductor compositions and layers and uses thereof. The invention has application particularly in the field of displays such as organic field effect transistors (OFETS), integrated circuits, organic light emitting diodes (OLEDS), photodetectors, organic photovoltaic (OPV) cells, sensors, lasers, memory elements and logic circuits.

Abstract: A layout design system includes a storage unit storing first and second standard cell designs, and a displacement module that arranges the first and second standard cell designs to generate an intermediate design in accordance with the chip design requirement. A first area for the first standard cell design and a second area for the second standard cell design are separated in the intermediate design by a filler design having no active area. Extended active areas are formed in the filler design in relation to the first standard cell design and second standard cell design.

Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.