Substantially Incomplete Signal Charge Transfer (e.g., Bucket Brigade, Etc.) Patents (Class 438/148)
  • Publication number: 20030109085
    Abstract: In order to realize a semiconductor device of enhanced TFT characteristics, a semiconductor thin film is selectively irradiated with a laser beam at the step of crystallizing the semiconductor thin film by the irradiation with the laser beam. By way of example, only driver regions (103 in FIG. 1) are irradiated with the laser beam in a method of fabricating a display device of active matrix type. Thus, it is permitted to obtain the display device (such as liquid crystal display device or EL display device) of high reliability as comprises the driver regions (103) made of crystalline semiconductor films, and a pixel region (102) made of an amorphous semiconductor film.
    Type: Application
    Filed: November 25, 2002
    Publication date: June 12, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Patent number: 6555409
    Abstract: In a method of fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer is formed on the substrate with the gate line assembly. A semiconductor layer, and an ohmic contact layer are sequentially formed on the gate insulating layer. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. The chrome-based under-layer of the conductive film is patterned through dry etching while using Cl2 or HCl as the dry etching gas.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 29, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Gab Kim, Mun-Pyo Hong
  • Patent number: 6509211
    Abstract: A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: January 21, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigenobu Maeda, Iijong Kim
  • Patent number: 6506635
    Abstract: In order to realize a semiconductor device of enhanced TFT characteristics, a semiconductor thin film is selectively irradiated with a laser beam at the step of crystallizing the semiconductor thin film by the irradiation with the laser beam. By way of example, only driver regions (103 in FIG. 1) are irradiated with the laser beam in a method of fabricating a display device of active matrix type. Thus, it is permitted to obtain the display device (such as liquid crystal display device or EL display device) of high reliability as comprises the driver regions (103) made of crystalline semiconductor films, and a pixel region (102) made of an amorphous semiconductor film.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: January 14, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20020182783
    Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 5, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Kengo Akimoto
  • Patent number: 6417531
    Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: July 9, 2002
    Assignee: NEC Corporation
    Inventor: Yasutaka Nakashiba
  • Publication number: 20020086463
    Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.
    Type: Application
    Filed: November 8, 2001
    Publication date: July 4, 2002
    Inventors: Theodore W. Houston, Keith A. Joyner
  • Patent number: 6380006
    Abstract: To obtain a reflowed resist mask 13, organic solvent is infiltrated into a resist mask 7 to reflow the resist mask 7 after first etching using the resist mask 7. As the volume of the resist mask is not reduced, heating is hardly required and in addition, the large viscosity is reduced, the area coated with the resist mask can be increased by a simple method before second etching, in addition, adhesion can be made satisfactory and as a result, wiring 11 having tapered structure can be easily formed.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 30, 2002
    Assignee: NEC Corporation
    Inventor: Shusaku Kido
  • Patent number: 6380005
    Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N−− semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N−− semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N−− semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: April 30, 2002
    Assignee: NEC Corporation
    Inventor: Yasutaka Nakashiba
  • Publication number: 20010041391
    Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.
    Type: Application
    Filed: March 21, 2001
    Publication date: November 15, 2001
    Applicant: FUJITSU, LTD.
    Inventors: Akito Hara, Kuninori Kitahara
  • Patent number: 6313003
    Abstract: A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as SixNy or SiON or TaN and TiN, is deposited over the surface of a semiconductor substrate, points of electrical contact have been provided in this semiconductor surface. A layer of IMD is deposited over the layer of insulation, an opening is created in the layer of IMD that aligns with and overlays a contact point over which a MIM capacitor is to be created. Under the second embodiment of the invention, a stack of three layers of a first layer of TaN followed by SiOx or SixNy followed by a second layer of TaN is used as the dielectric layer for the capacitor whereby the first layer of TaN is used as an etch stop for an opening that is etched for the creation of the upper plate of the capacitor.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: November 6, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Sheng-Hsiung Chen
  • Patent number: 6140156
    Abstract: A method for fabricating a photodiode is described in which a pad oxide layer and a silicon nitride layer are sequentially formed on a provided substrate. The silicon nitride layer, and the pad oxide layer and the substrate are sequentially patterned to form an opening in the substrate. A spacer is formed on the sidewall of the opening. With the spacer and the silicon nitride layer serving as a mask, the substrate is etched forming a trench in the substrate. An oxide plug is then formed filling the trench and the opening using the conventional shallow trench fabrication method. A P-well region and an N-well region are formed respectively on two sides of the trench.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: October 31, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Meng-Jin Tsai
  • Patent number: 6107124
    Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: August 22, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventors: Yong Park, Do Hyung Kim, Sang Ho Moon
  • Patent number: 6103564
    Abstract: A diode is formed by forming a PN junction region 6 with a p region 5 formed on a buried oxide film 19 side and an n region 7 formed on the surface side in a surface silicon layer 3 which is isolated by the buried oxide film 19 of an SOI substrate 1, providing a lightly doped p region 33 on one end side of the PN junction region 6 and a lightly doped n region 31 on an other end side, forming a heavily doped p region 13 and a heavily doped n region 9 at the respective surface portions of the lightly doped p region 33 and the lightly doped n region 31 in such a manner as not to contact the PN junction region 6, and providing two metal plates which respectively connect to the heavily doped p region 13 and the heavily doped n region 9.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: August 15, 2000
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Takashi Masuda
  • Patent number: 6093660
    Abstract: Disclosed is an inductively coupled plasma chemical vapor deposition method for depositing a selected thin film on a substrate from inductively coupled plasma, the method including the steps of: providing a vacuum reaction chamber including an interior bounded, in part by a dielectric shield, the dielectric shield having an amorphous silicon layer on its interior surface, and an antenna arranged outside the deposition chamber adjacent to the dielectric shield where RF power is applied; placing the substrate on a stage with the chamber; exhausting the vacuum reaction chamber leaving a vacuum state; introducing a reactant gas to the vacuum reaction chamber at a predetermined pressure; and applying RF power to the antenna, whereby inductively coupled plasma for deposition of a thin film from the reactant gas is formed within the vacuum chamber.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: July 25, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Jin Jang, Jae-gak Kim, Se-Il Cho