Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.

Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (25), above the semiconductor layer (23); forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: A method for manufacturing a biosensor includes forming a laminate of a first silicon oxide film and a polysilicon film on one surface of a silicon substrate; forming a second silicon oxide film on the other surface of the silicon substrate; forming a source electrode, a drain electrode, and a channel on the first silicon oxide film, the channel connecting the source electrode and the drain electrode; and removing the polysilicon film.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: A method for manufacturing a TFT substrate in which a channel length can be stably formed while the number of masks is reduced. The method includes processing a gate of the n-type TFT, a gate of the p-type TFT, and an upper capacitor electrode by using a half-tone mask instead of some of normal masks to reduce the number of masks, and changing impurity concentrations of semiconductor films located in regions which become a channel of the n-type TFT, a source and a drain of the n-type TFT, a channel of the p-type TFT, a source and a drain of the p-type TFT, and an lower capacitor electrode, by using a pattern of the half-tone mask and a normal mask.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract: A fabricating method of a TFT array substrate includes following steps: providing a substrate having a pixel region and a bonding pad region surrounding the pixel region; forming a patterned polysilicon layer within the pixel region on the substrate; forming a first patterned insulating layer to cover the patterned polysilicon layer; forming a first patterned transparent conductive layer on the first patterned insulating layer; forming a first metal layer on the first patterned transparent conductive layer; forming a second patterned insulating layer to cover the first metal layer; forming a second patterned transparent conductive layer on the second patterned insulating layer; forming a second metal layer on the second patterned transparent conductive layer; forming a third patterned insulating layer to cover the second metal layer; and forming a third patterned transparent conductive layer on the third patterned insulating layer.

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.

Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.

Abstract: A method of fabricating a TFT array substrate that prevents mobile ions from moving from a photoresist to channels of the TFT by the gate electrode of the TFT by performing photolithography processes for ion injection after forming gate electrode of TFT and, in addition, a method of fabricating a TFT array substrate that omits a photolithography process for forming a lower electrode of a storage capacitor by forming the lower electrode of the storage capacitor by a channel doping process for a PMOS TFT.

Abstract: A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.

Abstract: According to a method of manufacturing a semiconductor device of the present invention, a gate electrode is formed above a substrate, and a insulating film is formed above the gate electrode. Then, an amorphous semiconductor film is formed above the insulating film, laser annealing is performed on the amorphous semiconductor film, and the amorphous semiconductor film is changed to a crystalline semiconductor film. After that, hydrofluoric acid processing is performed on the crystalline semiconductor film, and an amorphous semiconductor film is formed above the crystalline semiconductor film where the hydrofluoric acid processing is performed so that pattern ends of the amorphous semiconductor film are arranged outside pattern ends of the crystalline semiconductor film and the amorphous semiconductor film contacts with the insulating film near the pattern ends.

Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Abstract: A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process, and then forming source and drain areas in the semiconductor substrate, and then removing the second dielectric film, and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate, and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract: In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs.

Abstract: A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer.

Abstract: A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photol

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced.

Abstract: Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays.

Abstract: An exemplary embodiment of a system comprises an active matrix organic electroluminescent device, having a substrate, and a plurality of scan lines and data lines disposed on the substrate, for defining a plurality of pixel regions. Each pixel structure comprises: a switching thin film transistor, a driving thin film transistor, and a storage capacitor. The switching TFT has a light-shielding layer adapted for preventing the sunlight from being incident into the switching TFT. The driving TFT is a bottom gate thin film transistor and have advantages of precisely controlling the current provided to the organic electroluminescent diode. Further, since the storage capacitor has a multilayer structure and occupies a reduced pixel area, the aperture ratio of the pixel structure can be increased.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.