Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region.

Abstract: To suppress an effect of metal contamination caused in manufacturing an SOI substrate. After forming a damaged region by irradiating a semiconductor substrate with hydrogen ions, the semiconductor substrate is bonded to a base substrate. Heat treatment is performed to cleave the semiconductor substrate; thus an SOI substrate is manufactured. Even if metal ions enter the semiconductor substrate together with the hydrogen ions in the step of hydrogen ion irradiation, the effect of metal contamination can be suppressed by the gettering process. Accordingly, the irradiation with hydrogen ions can be performed positively by an ion doping method.

Abstract: An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract: Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a well region within a substrate. A plurality of transistors is formed within and/or over the well region. The method further includes forming a first discharge device within the substrate. The first discharge device is coupled to the well region and a low voltage node. During subsequent processing, the first discharge device discharges charge from the well region.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract: A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.

Abstract: In at least one operation control TFT (27N, 27P) in a control circuit (27), an impurity of a type that generates an impurity level of a channel region (33c) is included in the channel region (33c) as a threshold adjustment impurity, and the concentration of the threshold adjustment impurity is made higher than the concentration of the threshold adjustment impurity in channel regions (33c) of other TFTs (21, 25, 28) of the same type, thus causing the absolute value of the threshold voltage to be greater than that of the other TFTs (21, 25, 28) of the same type.

Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.

Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

Abstract: In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device (100) is disclosed that is provided with a first P-type TFT (10a), a second P-type TFT (10b), a first N-type TFT (10c), and a second N-type TFT (10d), each having a channel region that is formed of polycrystalline silicon. When d1, d2, d3, and d4 respectively represent the concentrations of p-type impurities in the respective channel regions of the TFTs (10a to 10d), at least three values out of d1, d2, d3, and d4 are mutually different, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4.

Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.

Abstract: A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

Abstract: A method of manufacturing a butted junction CMOS inverter with asymmetric complementary FETS on an SOI substrate may include: forming a butted junction that physically contacts a first drain region of a first FET and a second drain region of a second complementary FET on the SOI substrate, where the butted junction is disposed medially to a first channel region of the first FET and a second channel region of the second complementary FET; implanting a first halo implant on only a source side of the first channel region, to form a first asymmetric FET; and forming a second halo implant on only a source side of the second channel region of the second complementary FET, to form a second asymmetric complementary FET.

Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract: Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.

Abstract: The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved.

Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.

Abstract: The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.

Abstract: SOI structures with silicon layers less than 20 nm thick are used to form ETSOI semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and lowers the drain induced bias and sub-threshold swings. The structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, during STI and contact formation.

Abstract: A system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified. The input signal can either be the result of photoabsorption process in the wavelengths greater than 950 nm or a low-level electrical signal. The discrete amplifier is an avalanche amplifier operable in a non-gated mode while biased in or above the breakdown region, and includes a composite dielectric feedback layer monolithically integrated with input signal detection and amplification semiconductor layers.

Abstract: A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an optically reflective layer overlying the NMOS transistor structure, forming a layer of tensile stress inducing material overlying the optically reflective layer, and curing the layer of tensile stress inducing material by applying ultraviolet radiation. Some of the ultraviolet radiation directly radiates the layer of tensile stress inducing material and some of the ultraviolet radiation radiates the layer of tensile stress inducing material by reflecting from the optically reflective layer.

Abstract: A method for fabricating a LCD having enhanced aperture ratio and brightness includes: forming a gate line, a gate electrode, a common electrode and a common line in a first mask process; depositing a gate insulating layer covering the gate line, the gate electrode and the common electrode; forming an active layer on the gate insulating layer, and an ohmic contact layer on the active layer in a second mask process; forming a data line, a source electrode, and a drain electrode facing the source electrode in a third mask process; depositing a protective layer over the data line, the source electrode and the drain electrode; forming a pixel contact hole in a fourth mask process; and forming a pixel electrode, wherein the pixel electrode is connected to the drain electrode through the pixel contact hole in a fifth mask process using a reverse tapered photo-resist pattern.

Abstract: Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g

Abstract: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state.

Abstract: A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

Abstract: A manufacturing method of a thin film transistor includes: forming semiconductor layers for a plurality of thin film transistors over a substrate; forming an insulating layer covering the semiconductor layers; and forming a metal layer over the insulating layer. The method further includes: patterning the metal layer to form mask patterns; doping first ions using a first mask pattern among the mask patterns into a first semiconductor layer among the semiconductor layers to simultaneously form source region/a drain regions and an active region of the first thin film transistor; and doping second ions using a second mask pattern among the mask patterns into a second semiconductor layer among the semiconductor layers to form a source region and a drain region of the second thin film transistor.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

Abstract: A purpose of the present invention is to reduce the driving voltage of a semiconductor device that includes an n-type TFT and a p-type TFT. Disclosed is a semiconductor device in which an n-channel type first thin film transistor (100) and a p-channel type second thin film transistor (200) are provided on the plane of a substrate (1). A first semiconductor layer (11) of the first thin film transistor (100) has a main portion, which is sandwiched between the upper surface and the lower surface of the first semiconductor layer (11), and an slanted portion, which is sandwiched by the side face and the lower surface of the first semiconductor layer (11). A second semiconductor layer (20) has a main portion, which is sandwiched between the upper surface and the lower surface of the second semiconductor layer (20), and a slanted portion, which is sandwiched between the side face and the lower surface of the second semiconductor layer (20).

Abstract: A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.

Abstract: The present invention provides a multi-working voltages CMOS device with single gate oxide layer thickness, gate work functions of CMOS transistors are regulated by implanting ions with different work functions into metal oxide dielectric material layers of the CMOS transistors, thus to realize different flat-band voltages under the condition of single dielectric layer thickness, and realize a multi-working voltages CMOS structure under the condition of single dielectric layer thickness. The present invention overcomes the process complexity of multiple kinds of gate dielectric layer thicknesses needed by traditional multi-working voltages CMOS, simplifies the CMOS process, makes the manufacturing procedure simple and easy to execute, reduces the preparation cost and is suitable for industrial production.

Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

Abstract: A thin film transistor substrate. The thin film transistor substrate includes a substrate, an adhesive layer on the substrate, and a semiconductor layer having a first doped region, a second doped region and a channel region on the adhesive layer. The thin film transistor substrate further includes a first dielectric layer on the semiconductor layer, a gate electrode overlapping the channel region, a second dielectric layer on the first dielectric layer and the gate electrode, a source electrode disposed on the second insulating layer, and a drain electrode spaced apart from the source electrode on the source electrode. The channel region is disposed between the first doped region and the second doped region, and has a transmittance higher than those of the first doped region and the second doped region.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Abstract: Methods for consistently reproducing channels of small length are disclosed. An ink composition comprising silver nanoparticles and a surface modification agent is used. The surface modification agent may also act as a stabilizer for the nanoparticles. A first line is printed which forms a modified region around the first line. A second line is printed, which is repelled from the modified region. As a result, a channel between the first line and the second line is formed.