Abstract: An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.

Abstract: An ultrasonic probe and an ultrasonic diagnosis device which can improve electrical safety for an operator are provided. The ultrasonic probe 2 has an insulating portion 62 between a mounting board 43 and a case 25. Since electrical leakage from the internal device of the ultrasonic probe 2 can be prevented, electrical safety of the ultrasonic probe 2 for the operator can be improved. A conductive film 61 is provided on the ultrasonic wave radiation side of a cMUT chip 20, and a conductive member 63 is provided along the insulating member 62. A conductive film 61 and a conductive member 63 are connected by a conductive member 64. A closed space having a ground potential is formed by the conductive film 61, the conductive member 63 and a coaxial cable 55 connected to ground. Main components or the body circuits of the ultrasonic probe 2 are contained in the closed space having the ground potential and shielded electrically from the outside.

Abstract: There is provided a resin dispensing apparatus for a light emitting device package and a method of manufacturing a light emitting device package using the same. The resin dispensing apparatus includes a resin dispensing part including a resin storage portion filled with a resin therein and a resin discharge portion combined with the resin storage portion and discharging the resin therefrom; a supporting part having a light emitting device package disposed on an upper surface thereof and electrically connected to the light emitting device package; a voltage applying part having both terminals respectively connected to the resin dispensing part and the supporting part to apply a voltage thereto; and a sensing part electrically connected to the resin dispensing part and the supporting part individually and sensing a contact between the resin dispensing part and the light emitting device package with an electrical signal.

Abstract: To provide an integrated circuit with functionality under environment with temperature lower than a working condition, the integrated circuit is designed to include a heating element incorporated with signal pins on a carrier, such as a lead frame, that supports a chip die and controlled by a heating control unit to increase temperature of the chip die. The heating control unit provides voltage for the heating element when a detecting unit detects that the temperature of the chip die falls below a predetermined temperature and a power control unit provide operation power for the chip die when the temperature of the chip die detected by the detecting unit reaches or falls above the predetermined temperature.

Abstract: A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: A method of combining LEDs in a packaging unit includes determining a color locus of a multiplicity of LEDs, classifying the LEDs into a plurality of different color locus ranges, each LED classified into a color locus range comprising the determined color locus of the respective LED, arranging the LEDs in the packaging unit such that the packaging unit contains a plurality of successive sequences respectively of a plurality of LEDs, wherein each sequence respectively has exactly one LED from each of the color locus ranges, and the LEDs of the different color locus ranges are respectively arranged in the same order within the sequences.

Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Abstract: Parts of electronic components are not exposed to temperature deviating from an appropriate operation temperature range when an electric characteristic test of a semiconductor module having an interposer substrate over which plural kinds of electronic components are mounted is carried out. A heat sink for an electronic component is incorporated in a lid of a test socket used for an electric characteristic test of an MCM. A heat dissipation sheet is attached to part of the bottom face of the heat sink and an adiabatic sheet is attached to another part. The heat dissipation sheet has thermal conductivity larger than the adiabatic sheet and transfers heat generated from an electronic component of a high heat value to the heat sink during operation. The adiabatic sheet inhibits the heat generated from an electronic component of high heat value from being transferred to another electronic component through the heat sink.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: Method and apparatus for bonding an electrical circuit component onto a substrate. A first electrically conductive bonding pad is formed on the component, and a second electrically conductive bonding pad is formed on the substrate. One of said first and second bonding pads is physically split into at least two parts, with electrical discontinuity between the two parts. An electrically conductive bond is formed between the first and second bonding pads such that electrical continuity is established from one part of the one bonding pad, through the other of the bonding pads, and through the second part of the one bonding pad. The integrity of the electrically conductive bond is evaluated by testing electrical continuity between the at least two parts.

Abstract: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: In a resin coating used for manufacturing an LED package including an LED element coated with resin containing phosphor, a light-transmitting member test-coated with resin for an emission characteristic measurement on a light-transmitting member placing section including a light source unit, a deviation between a measurement result of an emission characteristic of light emitted from the resin coated on the light-transmitting member measured by an emission characteristic measurement unit by irradiating the resin with excitation light emitted from the light source unit and a prescribed emission characteristic is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for an actual production is derived based on the deviation.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract: Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.

Abstract: A method is provided for assembling a stack of surface-mount devices (SMDs) on a substrate. The method provides a substrate, die, or printed circuit board (PCB) with a top surface having a landing pad and a first reference feature. An alignment jig is placed overlying the substrate top surface. The alignment jig second reference feature is aligned with respect to the substrate first reference feature. A first SMD is placed overlying the substrate landing pad. The first SMD third reference feature is aligned with respect to the alignment jig second reference feature. A second SMD is placed overlying the substrate top surface. Then, the alignment jig first boundary feature is mated with the second SMD second boundary feature. In response to the mating, the second SMD first interface is aligned over an underlying SMD active element.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: An electronic component mounting apparatus is capable of significantly reducing a warpage amount of an electronic component warped in a case of thermocompression bonding using a conductive adhesive agent having conductive particles and a low minimum melt viscosity where a thin electronic component having a thickness smaller than or equal to 200 ?m is mounted on a wiring board. In the mounting apparatus, an anisotropic conductive adhesive film having the minimum melt viscosity lower than or equal to 1.0×103 Pa·s is placed on a wiring board placed on a base, and an IC chip having a thickness smaller than or equal to 200 ?m is placed on the anisotropic conductive adhesive film. In the mounting apparatus, the IC chip is pressurized by a thermocompression bonding head having a compression bonding portion made of elastomer having a rubber hardness lower than or equal to 60, so that the IC chip is bonded onto the wiring board by thermocompression.

Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract: There is provided a method of manufacturing a light emitting diode (LED) package, including discharging a predetermined discharge amount of a phosphor-containing fluid resin to at least one LED package, and measuring color coordinates of white light emitted from the at least one LED package. The method also includes adjusting a discharge amount of the phosphor-containing fluid resin, based on a deviation between the measured color coordinates and target color coordinates, so as to obtain the target color coordinates. The method further includes discharging the adjusted discharge amount of the phosphor-containing fluid resin to another LED package;, and curing the phosphor-containing fluid resin dispensed to the another LED package.

Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, 1600, 1700. The assembly 400 uses no solder. Components 406, or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702. Assemblies may be mated 1800. Within the mated assemblies, items may be inserted including pins 2202a, 2202b, and 2202c, mezzanine interconnection devices 2204, heat spreaders 2402, and combination heat spreaders and heat sinks 2602. Edge card connectors 2802 may be attached to the mated assemblies.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, moulding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A method of manufacturing a light-emitting device which includes a light-emitting source by applying, onto the light-emitting source, a fluorescent resin which includes fluorescent particles and is stored in and discharged from an applicator, the method includes: measuring a first concentration which is a concentration of the fluorescent particles included in the fluorescent resin discharged from the applicator; and applying, onto the light-emitting source, the fluorescent resin in an application amount determined based on the first concentration which has been measured and reference data which indicates a relationship between a concentration of the fluorescent particles and an application amount of the fluorescent resin that enables the light-emitting device to have constant chromaticity.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.

Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.

Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

Abstract: A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.

Abstract: An apparatus includes a slider structure having a top surface and a bottom surface opposite from the top surface. The apparatus includes a waveguide with an input facet at the top surface and an output proximate the bottom surface. A laser having an output facet is positioned proximate the input facet of the waveguide and include a second plurality of pads facing a first plurality of pads on the top surface of the slider. A bonding material is disposed between individual ones of the first and second plurality of pads such that a reflow of the bonding material induces relative movement between the laser and the top surface to align the input and output facets.

Abstract: The present invention discloses a method of enhancing color rendering index (CRI) of a white light emitting diode (LED), and particularly discloses a method of enhancing CRI of a white LED by adding a blue-green (or aquamarine) phosphor which can emit a light having wavelength of 485 nm to 519 nm.

Abstract: A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.

Abstract: Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.

Abstract: A light emitting diode (LED) package comprises a LED, and a lead frame electrically connected to the LED. The lead frame includes a notch which has a predetermined size and a predetermined shape configured to separate a solder paste into two regions on either side of the notch when the solder paste is disposed on the lead frame.

Abstract: A liquid crystal display (LCD) module is disclosed, which comprises a thin film transistor (TFT) substrate and a color filter (CF) substrate disposed opposite to each other, and a liquid crystal layer sandwiched between the TFT substrate and the CF substrate. The TFT substrate comprises a plurality of transmission test units and a plurality of wires. The CF substrate comprises a plurality of curing test units insulated from each other, and each of the curing test units is electrically connected to one of the wires via one of the transmission test units. An LCD device and a manufacturing method of an LCD module are further disclosed. The LCD device, the LCD module and the manufacturing method thereof according to the present disclosure can avoid occurrence of arcing in the TFT substrate during the CVD process, thereby improving the product yield and reducing the manufacturing cost.

Abstract: A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.

Abstract: A method of increasing the operating life of a semiconductor device that is to be used in a harsh ionizing radiation environment including determining heating criteria for annealing the device; installing the device in an electronic apparatus; and heating the installed device with a local heating source in accordance with the heating criteria.

Abstract: A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective.