Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

Abstract: A semiconductor die is attached onto a substrate on a process platform during manufacturing of a semiconductor package. A dispenser dispenses an adhesive onto the substrate, and the semiconductor die is bonded onto the adhesive which has been dispensed onto the substrate with a bonding tool. Thereafter, a bond line thickness between a bottom surface of the semiconductor die and a top surface of the substrate on the process platform is measured using a measuring device.

Abstract: A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.

Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.

Abstract: A system and method for controlling temperature of a MEMS sensor are disclosed. In a first aspect, the system comprises a MEMS cap encapsulating the MEMS sensor and a CMOS die vertically arranged to the MEMS cap. The system includes a heater integrated into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. In a second aspect, the method comprises encapsulating the MEMS sensor with a MEMS cap and coupling a CMOS die to the MEMS cap. The method includes integrating a heater into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor.

Abstract: A system and method for providing a MEMS device with integrated electronics are disclosed. The MEMS device comprises an integrated circuit substrate and a MEMS subassembly coupled to the integrated circuit substrate. The integrated circuit substrate includes at least one circuit coupled to at least one fixed electrode. The MEMS subassembly includes at least one standoff formed by a lithographic process, a flexible plate with a top surface and a bottom surface, and a MEMS electrode coupled to the flexible plate and electrically coupled to the at least one standoff. A force acting on the flexible plate causes a change in a gap between the MEMS electrode and the at least one fixed electrode.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A solar cell module and a method of manufacturing the solar cell module are disclosed. The method in accordance with an embodiment of the present invention includes forming a conductive bump on a conductive pad formed on one surface of a solar cell, forming a circuit pattern on one surface of a transparent substrate, in which the circuit pattern corresponds to a position of the conductive bump, adhering the solar cell to the transparent substrate in such a way that the conductive bump is in direct contact with the circuit pattern, and forming a protective resin layer on one surface of the transparent substrate in such a way that the solar cell is covered. By using the above steps, a thinner solar cell module can be implemented while improving the manufacturing efficiency.

Abstract: A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.

Abstract: This relates to systems and methods for providing a system-on-a-substrate. In some embodiments, the necessary components for an entire system (e.g., a processor, memory, accelerometers, I/O circuitry, or any other suitable components) can be fabricated on a single microchip in “bare die” form. The die can, for example, be coupled to suitable flash memory through a substrate and flexible printed circuit board (“flex”). In some embodiments, the flex can extend past the substrate, die, or both, to allow additional, relatively large components to be coupled to the flex. In some embodiments, the die can be coupled to the flash memory through the flex and without a substrate. In some embodiments, component test points can be placed on the flash memory side of the substrate.

Abstract: A wafer level marking system is provided including: providing a wafer, a wafer frame, and a support tape; mounting the wafer and the wafer frame on the support tape; and marking the wafer through the support tape.

Abstract: A method is disclosed for the fabrication of a tunable radio frequency (RF) power output filter that includes fabricating a core body and then forming a plastically deformable metallic shell over the exterior surface of the core body.

Abstract: In one aspect, an organic light emitting diode (OLED) display that includes: a substrate; an organic light emitting element on the substrate; a thin film encapsulation layer on the substrate and covering the organic light emitting element; a polymer carpet layer directly on the thin film encapsulation layer; and a cover film directly on the polymer carpet layer is provided.

Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.

Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

Abstract: A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.

Abstract: A sensor apparatus includes a metal oxide semiconductor sensor and a housing having an internal chamber in which the sensor is disposed. The housing includes at least one window for the ingress of a gas into the internal chamber from an atmosphere exterior to the housing. A gas-selective barrier is disposed across the at least one window.

Abstract: Apparatuses including pre-forming conductive bumps on bonding pads for probing and wire-bonding connections and methods for making the same are disclosed. A method may include providing a microelectronic die including a conductive bump formed on a bonding pad, and an insulating layer formed on at least a portion of a surface of the conductive bump, and probing the conductive bump to test the microelectronic die. Other embodiments are also described.

Abstract: The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package.

Abstract: The present invention generally provides an apparatus and a method for automatically calibrating the placement of fragile substrates into a substrate carrier. Embodiments of the present invention also provide an apparatus and a method for inspecting the fragile substrates prior to processing to prevent damaged substrates from being further processed or broken in subsequent transferring steps. Embodiments of the invention also generally provide an apparatus and a method for determining the alignment and orientation substrates that are to be delivered into or removed from a substrate carrier. Embodiments of the invention further provide an apparatus and method for accurately positioning the substrate carrier for substrate loading. The substrate carriers are generally used to support a batch of substrates that are to be processed in a batch processing chamber.

Abstract: A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once.

Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.

Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it.

Abstract: A light-tuning method is provided. In the method, a filter material is first selected for filtering out unwanted light of a specific wavelength to obtain a transmittance spectrum. The transmittance spectrum is multiplied by an eye sensitivity function to obtain a filtered spectrum. The filtered spectrum has a wavelength range between 450 nm and 650 nm. According to a full width at half maximum (FWHM) wavelength range of the filtered eye sensitivity function, a phosphor is selected and a light-emitting spectrum of the phosphor is determined so that between the light-emitting spectrum of the phosphor and the filtered eye sensitivity function is an optimal matching degree.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: A method of manufacturing an integrated circuit, IC, package comprising radio frequency, RF, components, the method comprising: electrically connecting a printed circuit pattern on an external major surface of an IC assembly to an RF testing motherboard by bringing them together with an interposed adaptor layer, the adaptor layer comprising a double-sided PCB, printed circuit board, with conductive vias between its printed circuit layers; RF testing the IC assembly using the RF testing motherboard, while RF tuning components of the IC assembly; and separating the IC assembly and connecting its major surface to a solder ball grid array, BGA, which has substantially the same RF impedance as the adaptor at RF signal paths from the IC assembly to the BGA.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.

Abstract: An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties.

Abstract: The present invention provides a die bonder capable of stripping a die without fail, or a highly reliable die bonder or pick-up method using the die bonder. When a die to be stripped out of plural dies (semiconductor chips) bonded to a dicing film is to be tossed and stripped from the dicing film, the dicing film corresponding to predetermined positions out of the peripheral portion of the die is tossed to form stripping start points and then, the dicing film corresponding to portions other than the above predetermined positions is tossed to strip the die from the dicing film.

Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.

Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.

Abstract: A method of forming a longitudinally continuous photovoltaic (PV) module includes arranging strips of thin-film PV material to be spaced apart from and substantially parallel to each other. The method also includes laminating a bottom layer to a first surface of the strips of thin-film PV material, the bottom layer including multiple bottom layer conductive strips. The method also includes laminating a top layer to a second surface of the strips of thin-film PV material opposite the first surface, the top layer including multiple top layer conductive strips. Laminating the bottom layer to the first surface and laminating the top layer to the second surface includes serially and redundantly interconnecting the strips of thin-film PV material together by connecting each one of the strips of thin-film PV material to a different one of the bottom layer conductive strips and a different one of the top layer conductive strips.

Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract: A method for manufacturing a light emitting device includes: measuring at least one of each wavelength of the emitted light of the light emitting element, each optical output of the emitted light of the light emitting element, and each chromaticity of the mixed light emitted through the mixed resin in a manufacturing process of the light emitting device; and adjusting chromaticity for each light emitting device by performing a prescribed chromaticity adjustment with regard to the mixed resin, on basis of a result obtained in the measuring, so that the chromaticity of the mixed light falls within a preset prescribed range.

Abstract: An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.

Abstract: A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s).

Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.

Abstract: Provided is a test apparatus for testing a device under test, comprising a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test; a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package; a testing section that tests the devices under test packaged in the test packages; a removing section that removes the devices under test that have been tested from the test packages; and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.

Abstract: Disclosed are an embedded semiconductor device including a phase changeable random access memory element and a method of fabricating the same. A semiconductor chip including a main memory element and a supplementary memory element is integrated on a substrate, intrinsic chip data are obtained by electrically testing the semiconductor chip, and the semiconductor chip is packaged. The intrinsic chip data are written into the supplementary memory element before the packaging of the semiconductor chip, and a memory layer of the supplementary memory element is formed of a material exhibiting an improved data retention property under thermal environmental conditions as compared with a memory layer of the main memory element.

Abstract: A semiconductor device includes a semiconductor chip with a gate electrode, and a stress detecting element placed on a surface of the semiconductor chip, and which detects stress applied to the surface. The semiconductor device controls a control signal to be applied to the gate electrode in response to stress detected by the stress detecting element. The stress detecting element is preferably provided as a first stress detecting element which detects stress applied to a central portion of the semiconductor chip in plan view. The stress detecting element is preferably provided as a second stress detecting element which detects stress applied to a circumferential portion of the semiconductor chip in plan view.

Abstract: One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage).

Abstract: A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly.

Abstract: A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm.

Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad.

Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.