Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Abstract: The disclosure provides members formed from multiple layers as well as enclosures and electronic devices that include the members. The members include glass members formed from multiple layers of glass. In some cases, the members include a protruding feature provided over a camera assembly of the electronic device. The member may define one or more through-holes that extend through the protruding feature. The protruding feature may define a textured region that may be configured to provide a matte or glossy appearance.

Abstract: A biological detection chip, a biological detection device, and a detection method thereof are disclosed. The biological detection chip includes a first base substrate and a plurality of detection units arranged in an array along a row direction and a column direction on the first base substrate. Each of the plurality of detection units includes a thin film transistor and an electrode, the thin film transistor is on the first base substrate and includes a gate electrode, a source electrode, and a drain electrode, and the electrode is on a side of the thin film transistor away from the first base substrate and is connected to the drain electrode, and the electrode is configured to carry a biological material to be detected.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A semiconductor structure includes a first electrode, a second electrode over the first electrode, a third electrode over the second electrode, a first insulating layer between the first electrode and the second electrode, and a second insulating layer between the second electrode and the third electrode. The third electrode includes a first bottom surface and a second bottom surface. The first bottom surface and the second bottom surface are at different levels. A width of the first bottom surface is greater than a width of the second bottom surface.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: A display device includes: a substrate; a polycrystalline silicon film on the substrate; and a first buffer film between the substrate and the polycrystalline silicon film and having one surface contacting the polycrystalline silicon film and another surface opposite to the one surface, wherein the one surface of the first buffer film has a first root mean square (RMS) roughness range, and the first RMS roughness range is 1.5 nm or less.

Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

Abstract: A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

Abstract: A display device includes a substrate, a first semiconductor layer on the substrate, a first gate insulating film on the first semiconductor layer, a first conductive layer on the first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode, a second semiconductor layer on the first gate insulating film and at a different layer from the first semiconductor layer, a second gate insulating film on the first conductive layer and the second semiconductor layer, a second conductive layer on the second gate insulating film and including a second gate electrode and a second electrode of the capacitor, a second interlayer insulating film on the second conductive layer, and a third conductive layer on the second interlayer insulating film and including a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode.

Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Abstract: A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

Abstract: A display apparatus includes: a base substrate; a thin film transistor disposed on the base substrate and including an active pattern; an insulating layer disposed on the active pattern of the thin film transistor; a connection electrode disposed on the insulating layer, and electrically connected to the thin film transistor, wherein the connection electrode includes a curved wiring portion; a first via insulating layer covering the connection electrode; a first electrode disposed on the first via insulating layer; a light emitting layer disposed on the first electrode and at least partially overlapping the connection electrode; and a second electrode disposed on the light emitting layer.

Abstract: The disclosure provides members formed from multiple layers as well as enclosures and electronic devices that include the members. The members include glass members formed from multiple layers of glass. In some cases, the members include a protruding feature provided over a camera assembly of the electronic device. The member may define one or more through-holes that extend through the protruding feature. The protruding feature may define a textured region that may be configured to provide a matte or glossy appearance.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.

Abstract: A microelectronic device is formed by forming at least a portion of a substrate of the microelectronic device by one or more additive processes. The additive processes may be used to form semiconductor material of the substrate. The additive processes may also be used to form dielectric material structures or electrically conductive structures, such as metal structures, of the substrate. The additive processes are used to form structures of the substrate which would be costly or impractical to form using planar processes. In one aspect, the substrate may include multiple doped semiconductor elements, such as wells or buried layers, having different average doping densities, or depths below a component surface of the substrate. In another aspect, the substrate may include dielectric isolation structures with semiconductor material extending at least partway over and under the dielectric isolation structures. Other structures of the substrate are disclosed.

Abstract: Thin film core-shell fin and nanowire transistors are described. In an example, an integrated circuit structure includes a fin on an insulator layer above a substrate. The fin has a top and sidewalls. The fin is composed of a first semiconducting oxide material. A second semiconducting oxide material is on the top and sidewalls of the fin. A gate electrode is over a first portion of the second semiconducting oxide material on the top and sidewalls of the fin. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact over a second portion of the second semiconducting oxide material on the top and sidewalls of the fin. A second conductive contact is adjacent the second side of the gate electrode, the second conductive contact over a third portion of the second semiconducting oxide material on the top and sidewalls of the fin.

Abstract: The present application provides a method of manufacturing an array substrate, the array substrate, and a display device. In the method, a photoresist layer is removed by a plasma cleaning technique after performing etching to prevent a gate electrode of the array substrate from contacting a stripping solution, thereby preventing a metal layer of the gate electrode from being corroded by the stripping solution.

Abstract: An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

Abstract: A display device suitable for application is provided. A display device capable of displaying images with high quality and with low power consumption is provided. The display device includes a first display portion, a second display portion, a non-display portion, a first substrate, and a second substrate. The first substrate and the second substrate are provided to face each other with the first display portion, the second display portion, and the non-display portion provided therebetween. The first display portion and the second display portion are provided apart from each other with the non-display portion therebetween. A plurality of liquid crystal elements are arranged in a matrix in the first display portion. A plurality of light-emitting elements are arranged in a matrix in the second display portion. The liquid crystal element reflects light to the second substrate side. The light-emitting element emits light to the second substrate side.

Abstract: In embodiments of the present disclosure, there is provided a display substrate assembly including: a base substrate; a light shielding layer on the base substrate; and an active layer of a thin film transistor, above the base substrate. An orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthographic projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer includes an ion-doped amorphous silicon layer. In embodiments of the present disclosure, there is also provided a method of manufacturing a display substrate assembly and a display apparatus including the display substrate assembly.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.

Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.

Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

Abstract: A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.

Abstract: A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light.

Abstract: A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

Abstract: A fin field effect transistor (finFET) and a method of fabricating the finFET. The method includes forming one or more fins above a substrate in a channel region, depositing a first insulating material conformally on the one or more fins and the substrate, and depositing a second insulating material over the first insulating material in non-channel regions adjacent to the channel region. A selective etch of the first insulating material in the channel region is performed to form a trench. The trench is filled with the second insulating material. The second insulating material in the channel region is adjacent to the first insulating material in the non-channel regions.

Abstract: An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.

Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

Abstract: The EL substrate includes semiconductor layers of TFTs, a pixel electrode, and an upper part electrode of a Cs section which are provided on a gate insulating film. The semiconductor layers are covered with a protective film which has openings via which the pixel electrode and the upper part electrode are exposed. The semiconductor layers are an oxide semiconductor layer, and the pixel electrode and the upper part electrode are reduction electrodes of the oxide semiconductor layer.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.