Including Recrystallization Step Patents (Class 438/166)
  • Patent number: 7927935
    Abstract: Laser beams emitted by a plurality of laser sources are divided into a plurality of sub-beams, which are irradiated onto selected portions of an amorphous semiconductor on a substrate to crystallize the amorphous semiconductor. A difference in diverging angles between the laser beams is corrected by a beam expander. The apparatus includes a sub-beam selective irradiating system including a sub-beam dividing assembly and a sub-beam focussing assembly. Also, the apparatus includes laser sources, a focussing optical system, and a combining optical system. A stage for supporting a substrate includes a plurality of first stage members, a second stage member disposed above the first stage members, and a third stage member 38C, rotatably disposed above the second stage to support an amorphous semiconductor.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 19, 2011
    Assignees: Sharp Kabushiki Kaisha, Japan Laser Corporation
    Inventors: Nobuo Sasaki, Tatsuya Uzuka
  • Patent number: 7923316
    Abstract: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Takashi Noguchi, Se-young Cho, Do-young Kim, Jang-yeon Kwon
  • Patent number: 7923311
    Abstract: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor device further includes source and drain electrodes formed on the pair of impurity doped second semiconductor layers, wherein the pair of impurity doped second semiconductor layers extend beyond inner sides edges of the source and drain electrodes so that a stepped portion is formed from an upper surface of the source and drain electrodes to a surface of the first semiconductor film.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 7923317
    Abstract: To crystallize a material, a thin layer of amorphous or polycrystalline material is deposited on at least one area of the surface of a top part of a substrate. A metal layer is then deposited on at least one area of the thin layer. Thermal treatment is then performed to enable crystalline growth of the material of the thin layer, resulting in: a rapid temperature increase of the top part of the substrate until liquid or overmelted liquid state is achieved, and heat transfer from the interface between the top part of the substrate and the thin layer to the interface between the thin layer and the metal layer.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: April 12, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Philippe Bouchut
  • Patent number: 7919777
    Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuck Lim, Young-soo Park, Wenxu Xianyu, Young-kwan Cha
  • Patent number: 7919366
    Abstract: A laser crystallization method in which an amorphous silicon thin film 2 formed on a substrate 1 is irradiated with a laser beam, the method including the steps of providing the amorphous silicon thin film 2 with an absorbent to form an absorbent layer 3 on the desired specific local areas of the amorphous silicon thin film 2 and laser annealing for crystallizing the specific local areas of the amorphous silicon thin film 2 by irradiating the amorphous silicon thin film 2 including the specific local areas with a semiconductor laser beam L having a specific wavelength absorbable by the absorbent layer 3 and unabsorbable by the amorphous silicon thin film 2 for heating the absorbent layer 3.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: April 5, 2011
    Assignees: Osaka University, The Japan Steel Works, Ltd.
    Inventors: Takahisa Jitsuno, Keiu Tokumura, Ryotaro Togashi, Toshio Inami, Hideaki Kusama, Tatsumi Goto
  • Publication number: 20110073918
    Abstract: A semiconductor device includes a thin-film transistor 126 and a thin-film diode 127. The respective semiconductor layers 109t and 109d of the thin-film transistor 126 and the thin-film diode 127 are portions of a single crystalline semiconductor layer obtained by crystallizing the same amorphous semiconductor film. The semiconductor layer 109t of the thin-film transistor 126 does include a catalyst element that promotes crystallization of the amorphous semiconductor film. But the semiconductor layer 109d of the thin-film diode 127 includes substantially no catalyst elements.
    Type: Application
    Filed: May 26, 2009
    Publication date: March 31, 2011
    Inventor: Naoki MAKITA
  • Patent number: 7915103
    Abstract: The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: March 29, 2011
    Assignee: Chimei Innolux Corporation
    Inventors: Chun-Yen Liu, Chang-Ho Tseng
  • Patent number: 7915099
    Abstract: The speed of the laser scanned by the scanning means such as a galvanometer mirror or a polygon mirror is not constant in the center portion and in the end portion of the scanning width. As a result, the object, for example an amorphous semiconductor film, is irradiated with the excessive energy and therefore there is a risk that the amorphous semiconductor film is peeled. In the present invention, in the case where the laser spot of the energy beam output continuously on the irradiated object is scanned by moving it back and forth with the use of the scanning means or the like, the beam is irradiated to the outside of the element-forming region when the scanning speed of the spot is not the predetermined value, for example when the speed is not constant, and accelerates, decelerates, or is zero, for example in the positions where the scanning direction changes, or where the scanning starts or ends.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka, Hidekazu Miyairi
  • Patent number: 7910414
    Abstract: A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 22, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Dong Choi, Sang-Gul Lee, Seong-Moh Seo, Jun-Min Lee, Byung-Chul Ahn
  • Patent number: 7910416
    Abstract: In annealing of a non-single crystal silicon film by a linear laser beam, it is performed so as irradiation tracks caused by the linear laser beam do not remain in the silicon film. Laser light is partitioned by an integrally formed cylindrical array lens, and is composed into a single uniform laser beam on an irradiation surface by a cylindrical lens and a doublet cylindrical lens. The integrally formed cylindrical array lens is used, and therefore cylindrical lenses structuring this array lens can be made very fine. It thus becomes possible to partition the laser light into a large number of partitions, and the uniformity of the laser beam on the irradiation surface is increased. Very few laser irradiation tracks remain on the silicon film annealed by the very uniform laser beam.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Patent number: 7910920
    Abstract: A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-chul Park, Young-soo Park, Sun-Il Kim
  • Patent number: 7906382
    Abstract: A method of crystallizing an amorphous semiconductor thin film formed on a substrate is provided. The method includes the steps of: forming a gate insulation film and a gate electrode on an amorphous semiconductor thin film; locally forming first and second crystallization induced metal patterns for inducing crystallization of the amorphous semiconductor thin film, on part of the amorphous semiconductor thin film spaced at a predetermined off-set distance from the gate insulation film; ion-injecting impurities into the substrate to thus define a source/drain region; forming a protection film on the whole surface of the substrate; and heat-treating the substrate in the air to thereby crystallize the amorphous semiconductor thin film.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 15, 2011
    Assignee: Neopoly Inc.
    Inventor: Woon Suh Paik
  • Patent number: 7906415
    Abstract: An electronic device including: (a) a semiconductor layer including crystalline zinc oxide; and (b) an electrode including a suitable amount of zinc, indium, or a mixture thereof.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 15, 2011
    Assignee: Xerox Corporation
    Inventors: Yuning Li, Beng S. Ong
  • Patent number: 7902010
    Abstract: A mask for sequential lateral solidification (SLS) processes including at least one first window, one second window, one third window, and one fourth window is provided. Each window has a length extending longitude on the mask. The second window is aligned to the first window. The width of the first window is greater than that of the second window. The fourth window is aligned to the third window. The width of the third window is greater than that of the fourth window.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: March 8, 2011
    Assignee: AU Optronics Corp.
    Inventor: Ming-Wei Sun
  • Patent number: 7902009
    Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Danielle Simonelli, Anand Murthy
  • Patent number: 7902008
    Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Igor Peidous, Mario M. Pelella
  • Patent number: 7902002
    Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20110050733
    Abstract: To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. In the semiconductor device, a crystalline oxide is used as an N-type transistor and the electron carrier concentration of the crystalline oxide is less than 2×1017/cm3. Furthermore, the crystalline oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca, and the atomic ratio In [In] and the positive divalent element [X][X]/([X]+[In]) is 0.0001 to 0.13.
    Type: Application
    Filed: February 6, 2008
    Publication date: March 3, 2011
    Applicant: IDEMITSU KOSAN CO., LTD
    Inventors: Koki Yano, Kazuyoshi Inoue, Futoshi Utsuno, Masashi Kasami
  • Publication number: 20110037073
    Abstract: A thin film transistor (TFT), an OLED device having the TFT and a method of fabricating the same and a method of fabricating an organic light emitting diode (OLED) display device that includes the TFT. The method of fabricating a TFT includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer pattern on the buffer layer, forming a metal layer on an entire surface of the substrate, forming a semiconductor layer by applying an electrical field to the metal layer to crystallize the amorphous silicon layer pattern, forming source and drain electrodes connected to the semiconductor layer by patterning the metal layer, forming a gate insulating layer on the entire surface of the substrate, forming a gate electrode on the gate insulating layer to correspond to the semiconductor layer and forming a protective layer on the entire surface of the substrate.
    Type: Application
    Filed: March 5, 2010
    Publication date: February 17, 2011
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: JI-SU AHN, WON-PIL LEE
  • Publication number: 20110037074
    Abstract: A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, source and drain electrodes directly on the semiconductor layer, each of the source and drain electrodes including at least one hole therethrough, a gate insulating layer on the substrate, and a gate electrode on the gate insulating layer and corresponding to the semiconductor layer.
    Type: Application
    Filed: March 12, 2010
    Publication date: February 17, 2011
    Inventors: Ji-Su Ahn, Hoon-Kee Min
  • Patent number: 7889548
    Abstract: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Wook Jeong, Jun-Hyok Kong, Ji-Hye Yi, Beak-Hyung Cho
  • Publication number: 20110033992
    Abstract: A thin film transistor (TFT) having improved characteristics, a method for fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT is constructed with a substrate, a semiconductor layer disposed on the substrate and including a channel region, source and drain regions, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer and corresponding to the channel region, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer. The channel region is made from polycrystalline silicon (poly-Si), and the source and drain regions are made from amorphous silicon (a-Si). The polycrystalline silicon of the channel region is formed by crystallizing amorphous silicon using Joule's heat generated by the gate electrode.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventor: In-Young Jung
  • Patent number: 7879664
    Abstract: A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a second active layer in the peripheral region by etching the polycrystalline silicon film, forming a first gate electrode over the first active layer, a second gate electrode over the second active layer and a gate line connected to the first gate electrode, and forming first source and drain electrodes connected to the first active layer, second source and drain electrodes connected to the second active layer and data line connected to the first source electrode. Further, the second gate electrode overlaps the first active layer to form a first channel region, and the first channel region is formed inside one of the grains.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: February 1, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Yun-Ho Jung
  • Patent number: 7879722
    Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: February 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Matsuda, Takashi Ide, Hiroshi Kimura
  • Publication number: 20110020990
    Abstract: A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no gram boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film.
    Type: Application
    Filed: August 9, 2010
    Publication date: January 27, 2011
    Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
  • Publication number: 20110017997
    Abstract: Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon.
    Type: Application
    Filed: May 28, 2010
    Publication date: January 27, 2011
    Inventors: Arvind Kamath, Michael Kocsis, Kevin McCarthy, Gloria Man Ting Wong
  • Patent number: 7875508
    Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Publication number: 20110014755
    Abstract: A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 ? on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Tae-Hoon YANG, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park, Kil-Won Lee
  • Publication number: 20110014756
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: Samsung Mobile Display Co., Ltd
    Inventors: Byoung-Keon PARK, Tae-hoon Yang, Jin-Wook Seo, Sei-Hwan Jung, Ki-Yong Lee
  • Patent number: 7871907
    Abstract: A mask includes a primary opaque pattern and a number of clusters of secondary opaque patterns. The primary opaque pattern defines a number of strip transparent slits whose extending directions are substantially the same. The clusters of the secondary opaque patterns are connected to the primary opaque pattern, and each of the clusters of the secondary opaque patterns is disposed in one of the transparent slits, respectively. Each of the clusters of the secondary opaque patterns includes a number of secondary opaque patterns, and extending directions of at least a portion of the secondary opaque patterns and the extending directions of the transparent slits together form included angles that are not equal to about 90°.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: January 18, 2011
    Assignee: Au Optronics Corporation
    Inventor: Ming-Wei Sun
  • Patent number: 7871910
    Abstract: A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Jung Lee
  • Patent number: 7863162
    Abstract: A manufacturing method of a semiconductor device in which the oxygen and carbon concentrations are reduced at the interface of each layer making up the semiconductor multilayer film. A first semiconductor layer is formed on a single-crystal substrate in a first reactor; the substrate is transferred from the first reactor to a second reactor through a transfer chamber; and a second semiconductor layer is formed on the first semiconductor layer in the second reactor. During substrate transfer, hydrogen is supplied when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is less than the number of surface atoms of the first semiconductor layer, and the supply of hydrogen is stopped when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is greater than the number of surface atoms of the first semiconductor layer.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: January 4, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Isao Suzumura, Katsuya Oda
  • Patent number: 7863621
    Abstract: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on the polycrystalline silicon layer.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: January 4, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
  • Publication number: 20100330752
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 30, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Publication number: 20100330753
    Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee, Byeong-Chan Lee, InSoo Jung
  • Patent number: 7858455
    Abstract: A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for a channel formation region, the microcrystalline semiconductor layer is formed of a stacked layer of a microcrystalline semiconductor film which is formed by a deposition method and can be a nucleus of crystal growth and an amorphous semiconductor film; a conductive film and a semiconductor film which forms a source region and a drain region and to which an impurity imparting one conductivity is added are formed over the amorphous semiconductor film; and the conductive film is irradiated with laser light.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: December 28, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7855106
    Abstract: An improved type thin film semiconductor device and a method for forming the same are described. That is, in a thin film semiconductor device such as TFT formed on an insulating substrate, it is possible to prevent the intrusion of a mobile ion from a substrate or other parts, by forming the first blocking film comprising a silicon nitride, an aluminum oxide, an aluminum nitride, a tantalum oxide, and the like, under the semiconductor device through an insulating film used in a buffering, and then, by forming the second blocking film on TFT, and further, by covering TFT with said first and second blocking films.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: December 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 7851277
    Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7851802
    Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Seon-mi Yoon, Sang-yoon Lee, Jae-young Choi, Hyeon-jin Shin, Myung-kwan Ryu, Tae-sang Kim, Jang-yeon Kwon, Kyung-seok Son, Ji-sim Jung
  • Patent number: 7842565
    Abstract: The present invention provides a beam homogenizer for homogenizing energy distribution by making the distance between lenses small to shorten the optical path length with the use of an array lens of an optical path shortened type, and a laser irradiation apparatus using the beam homogenizer. The beam homogenizer is equipped with a front side array lens of an optical path shortened type whose second principal point is positioned ahead on a beam incidence side, a back side array lens of an optical path shortened type whose first principal point is positioned behind on a beam emission side, and a condensing lens, wherein the distance between the second principal point of the front side array lens and the first principal point of the back side array lens is equal to the focal length of the back side array lens.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 30, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 7842564
    Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Hirokazu Ishida, Yoshio Ozawa, Takashi Suzuki, Fumiki Aiso, Makoto Mizukami
  • Patent number: 7838397
    Abstract: In a laser annealing process: the first to fourth sections of a bandlike area of a nonmonocrystalline semiconductor film are consecutively scanned and irradiated with laser light so as to produce a fused region in the bandlike area, where the fourth section contains a portion required to have higher crystallinity than other portions of the bandlike area. In the first section, the width of the fused region is substantially uniform. In the second section, the width of the fused region is stepwise or continuously decreased from the width of the fused region in the first section. In the third section, the width of the fused region is stepwise or continuously increased from the width of the fused region at the boundary between the second and third sections. In the fourth section, the width of the fused region at the boundary between the third and fourth sections is substantially uniformly maintained.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: November 23, 2010
    Assignee: FUJIFILM Corporation
    Inventor: Atsushi Tanaka
  • Patent number: 7838352
    Abstract: A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no grain boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: November 23, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
  • Patent number: 7833851
    Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Koichiro Tanaka
  • Patent number: 7833826
    Abstract: After a gate oxide film 10 has been formed on a silicon substrate G, a first step of forming a microcrystalline silicon film by high electron density plasma of an electron temperature of 2.0 eV or less and a second step of forming an ultra-microcrystalline silicon film by high electron density plasma of an electron temperature higher than 2.0 eV are repeated. A stacked-layer film 20 of the ultra-microcrystalline silicon film and the microcrystalline silicon film is thereby formed. With the film formation method described above, at least one of an n-channel thin-film transistor and a p-channel thin-film transistor with the stacked-layer film 20 functioned as an active layer may be manufactured.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Shinsuke Oka
  • Patent number: 7820466
    Abstract: A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor layer having a first crystal growth in a lateral direction, and a pixel TFT disposed in the pixel area, the pixel TFT including a second semiconductor layer having a second crystal isotropic growth.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Na Jo, Chi-Woo Kim, Young-Jin Chang, Jae-Beom Choi
  • Patent number: 7820531
    Abstract: A method of manufacturing a semiconductor device includes the steps of: modifying a semiconductor film by applying a laser beam; and forming a semiconductor device on the modified semiconductor film. In the step of modifying the semiconductor film, the laser beam and the substrate are moved relative to each other in a first direction and a second direction which is opposite to the first direction, a change in an optical characteristic between an area irradiated with the laser beam and an area which is not irradiated with the laser beam in the substrate or an optical characteristic of the irradiated area is measured in each of the first and second directions, and irradiation power of the laser beam is modulated so that the difference between a measurement result in the first direction and a measurement result in the second direction lies in a predetermined range.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: October 26, 2010
    Assignee: Sony Corporation
    Inventors: Goh Matsunobu, Koichi Tatsuki, Yoshio Inagaki, Nobuhiko Umezu, Koichi Tsukihara
  • Patent number: 7816736
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7815734
    Abstract: Provided are a thin film transistor and method of fabricating the same, in which an amorphous silicon layer is formed on a substrate, a capping layer containing a metal catalyst having a different concentration according to its thickness is formed on the amorphous silicon layer, the capping layer is patterned to form a capping layer pattern, and the amorphous silicon layer is crystallized, such that the density and position of seeds formed at an interface between the amorphous silicon layer and the capping layer pattern is controlled, thereby improving the size and uniformity of grains, and in which polycrystalline silicon of desired size and uniformity is selectively formed at a desired position by one crystallization process, resulting in a thin film transistor having excellent and desired properties.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: October 19, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jin-Wook Seo, Tae-Hoon Yang, Ki-Yong Lee