Abstract: A method of forming a landed polysilicon plug in a self-aligned contact. A substrate having a plurality of gate electrodes thereon is provided. Before forming the self-aligned contact window, a dielectric liner layer conformal to a surface profile of the substrate and the gate electrodes is formed. An inter-layer dielectric layer is next formed over the dielectric liner layer. High etching selectivity ratio between the inter-layer dielectric layer and the dielectric liner layer is chosen, and thus the dielectric liner layer is used as an etching stop layer in the process of etching out the self-aligned contact window. After a polysilicon layer that fills the self-aligned contact window and covers the dielectric layer is formed, planarization is carried out to form the landed polysilicon plug having a desired thickness.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: There is disclosed a field effect transistor having a two-stage recess structure formed upon an InP substrate and showing stable device characteristics and a low contact resistance. The FET is manufactured as follows. Upon an InP substrate 101, a channel layer 103, electron supply layers 104 and 105, an undoped InAlAs Schottky layer 106, an n-type InAlAs first cap layer 107 and an n-type InGaAs second cap layer 108 are formed in succession, following which a second recess opening 111 is formed by etching from the surface of the second cap layer to just the surface of said Schottky layer or further to a level to remove a part of the Schottky layer. A first recess opening 110 is formed by side-etching the second cap layer using an etchant of which etching selectively of InGaAs over InAlAs is 30 or more.

Abstract: A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device includes a transistor configured to control the emission of electrons from an emitter.

Abstract: A manufacturing method that prevents an enhanced diffusion while preventing channeling from occurring, and forms a local channel having a steep impurity concentration distribution with precise positioning. After forming a sacrifice film on the surface of a silicon substrate, ion implantation is performed from a perpendicular direction through a resist film mask to form a local channel. The thickness of the sacrifice film is greater than or equal to 10 nm and less than or equal to 100 nm. Indium is used as an ion species of the ion implantation.

Abstract: A manufacturing method of a liquid crystal display is provided. The liquid crystal display having a picture element electrode formed on the uppermost layer of a structure is capable of reducing connection resistance between picture element electrode and drain electrode through interlayer insulating film. At the time of forming the picture element electrode, ITO film can be patterned into a desirable pattern without short circuit between assembled terminals in one etching process. In the process of forming a contact hole 112 for connecting the picture element electrode 113 and the drain electrode 108 on the interlayer insulating film 111 and on the passivation film 110, a dry etching condition is established so that after the ashing process using O2 gas to remove residue on the bottom of the contact hole 112, an etching process using fluorine gas+O2 gas etc. is performed to reduce irregularity on the surface of the interlayer insulating film 111.

Abstract: A method of fabricating an integrated circuit with a gate structure comprised of an oxide/polysilicon/metal stack. The method includes forming the gate structure by using a metal plug as a hard mask in place of a hard mask produced using photolithography. Thus, linewidth limitations of conventional photolithography do not apply. Specifically, the method includes providing a pattern over a semiconductor substrate; partially filling the pattern with a polysilicon material such that a trench is left in the polysilicon material, and filling the trench in the polysilicon material with metal to form a plug. After forming the materials, excess materials are removed leaving the gate structure.

Abstract: The invention is a method for fabricating a pseudomorphic HEMT transistor structure with a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer, and an ohmic contact layer on the transition layer. A double recess structure is disposed through the ohmic layer into the transition layer in which one or two layers of INYGa1−YAs are used as etch-stop layers to define the depth of the recess(es).

Abstract: A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Abstract: In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so small that reproducibility of parameters can become problematic. Specifically, the gate dielectric, typically silicon nitride, silicon oxide or silicon nitride, of a gate structure is nearing the point where the required thickness of the gate dielectric to provide the selected electric field in the channel region is implemented with a few to several atomic layers. In order to improve parameter reproducibility, a dielectric material, such TaO5 or a ferroelectric material, is used as a gate dielectric. TaO5 and the ferroelectric materials have a dielectric constant an order of magnitude higher than the material typically used in the past. Using these materials, the gate dielectric can be proportionately thicker, thereby improving the parameter reproducibility.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region.

Abstract: An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After removing the first resist layer, a second resist layer having second resist opening portions are formed. One of the second resist opening portions is provided to expose the substrate, and a recess is formed in the substrate through the opening portion. Further, the insulating layer exposed from the other of the second resist opening portions is removed. Then, an electrode member for gate, source, and drain electrodes is deposited on the substrate. As a result, variations in intervals between the gate and drain electrodes and between the gate and source electrodes can be reduced.

Abstract: A manufacturing method of compound semiconductor field effect transistor capable of enhancing a gate/drain withstand voltage includes a step of forming a channel layer by implanting ions into the surface of a semi-insulating compound semiconductor substrate and a step of performing a first thermal treatment for removing crystalline defects on the surface of the channel layer. This method also includes a step of forming a compound semiconductor epitaxial layer by use of an epitaxial method on a region covering the channel layer, a step of forming a gate electrode within a region on the epitaxial layer just above the channel layer and a step of forming a source region and a drain region in the substrate. A concentration of the impurity for forming the channel layer at an interface between the channel layer and the epitaxial layer is 45% or under of the highest concentration when forming the channel layer.

Abstract: A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication.To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in the trench; a gate electrode aligned on the semiconductor layer on one side of the trench; and an impurity region formed in the semiconductor layer adjacent the gate electrode on one side of the trench, and an impurity region also formed in the semiconductor layer on the other side of the trench.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a source region (44) and a drain region (45) that contact the corners (13) of the pedestal structure (16). Electrical connection to the source region (44) and the drain region (45) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).

Abstract: The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them.

Abstract: A method of fabricating an FET includes forming an active layer including a low dopant concentration layer, forming a recess in the active layer so that the bottom of the recess is present within the low dopant concentration semiconductor layer, forming side walls in the recess, and forming a gate electrode in the-recess using the side walls as masks. The gate length can be precisely reduced by the side walls. Further, even when the active layer is anisotropically etched to form the side walls, the low dopant concentration semiconductor layer is subjected to the etching. Therefore, a part of the active layer where a greater part of channel current flows is not adversely affected by the etching. Therefore, any variation in the thickness of the active layer does not vary the channel current of the transistor.

Abstract: A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.

Abstract: A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.

Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.

Abstract: Method for manufacturing a metal semiconductor field-effect transistor (MESFET) in which a gate area contacting a semiconductor surface is diminished and a gate cross area is increased, to improve frequency characteristics of a device is disclosed, including the steps of: forming an n-type GaAs layer and a heavily doped n.sup.+ -type GaAs layer on a substrate, sequentially; forming a first insulating layer on the heavily doped n.sup.

Abstract: Field-effect transistors are formed on a substrate having silicided elements including diffusion (source and drain) regions and polysilicon gates. The silicided surfaces of these elements have low ohmic resistance and are used to provide interconnection between contacts that are spaced from each other, thereby freeing routing areas for other interconnections. The diffusion regions of adjacent transistors have edges that face each other, and are formed with indentations which constitute portions of a substrate tap area. The low ohmic resistance of the silicided surfaces of the diffusion regions enables the substrate tap area to be cut out of the diffusion regions without degrading the electrical performance of the transistors, thereby providing a substantial reduction in the space required for the transistors on the substrate.

Abstract: A fabrication method of a compound semiconductor FET that enables to produce source/drain electrodes and a gate electrode at any positions flexibly without increase of the number of necessary process steps. First, a compound semiconductor substructure having on its surface first regions on which source/drain electrodes are formed respectively and a second region on which a gate electrode is formed is prepared. A patterned mask film is then formed on the surface of the substructure. The mask film has first windows for the source/drain electrodes and a second window for the gate electrode. A conductor film is selectively formed on the surface of the substructure using the patterned mask film as a mask. The conductor film contains first parts placed on the first regions through the respective first windows of the mask film and second part placed on the second region through the second window of the mask film.

Abstract: A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and RC time delay constants, and thereby improves circuit performance. The method consists of forming FETs having gate electrodes and interconnecting lines from a multilayer made up of a doped first polysilicon layer, a first silicide layer (WSi.sub.2), and a doped second polysilicon layer. After patterning the multilayer to form the gate electrodes, a titanium (Ti) metal is deposited and annealed to form a second silicide layer on the gate electrodes, and simultaneously forms self-aligned Ti silicide contacts on the source/drain areas. The latitude in overetching the contact openings in an insulating (PMD) layer to the gate electrodes extending over the field oxide area is increased, and the contact resistance (R.sub.c) is reduced because of the presence of the WSi.sub.