Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manufacturing period thereof is shortened. A feature is that a gate electrode is formed of conductive films of plural layers, and by using the selection ratio of those at the time of etching, the concentration of an impurity region formed in an active layer is adjusted.

Abstract: The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2+) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Abstract: A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on the bulk semiconductor substrate. The top surface of the donor wafer is bonded to the top surface of the target wafer. The strained silicon layer is then separated from the donor wafer so that the strained silicon layer adheres to the target wafer. The bond between the strained silicon layer and the target wafer can then be strengthened.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: The invention relates to a TFT device, a method of manufacturing the same, and a TFT substrate and a display having the same and provides a TFT device having good characteristics and high reliability, a method of manufacturing the same, and a TFT substrate and a display having the same. A metal thin film is formed on a gate insulation film. Patterning is performed to remove the metal thin film on a semiconductor layer to become source and drain regions of an n-type TFT. Phosphorous ions are implanted using the patterned metal thin film as a mask to form the source and drain regions. The patterned metal thin film is further patterned to form a gate electrode of the n-type TFT. Phosphorous ions are implanted using the gate electrode as a mask to form LDD regions between the source and drain regions and a channel region.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

Abstract: A method for making a metal-insulator-semiconductor field effect transistor (MISFET) having an oxidized aluminum nitride gate insulator formed on a silicon or gallium nitride substrate. The method of making the MISFET comprises the steps of depositing an aluminum nitride layer on the entire upper surface of the silicon or gallium nitride substrate. Subsequently, the aluminum nitride layer is oxidized to convert it into an oxidized aluminum nitride layer which acts as a gate insulator of the MISFET. Portions of the oxidized aluminum nitride layer are etched to form a plurality of openings that expose regions to become the source and drain regions of the substrate. The source and drain regions are formed in the plurality of openings by conventional techniques including diffusion and ion-implantation. Finally, a metal layer is formed in the plurality of openings of the oxidized aluminum nitride layer, wherein the metal layer contacts the source and drain regions of the substrate.

Abstract: A semiconductor display device which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask. and thus impurity concentrations of the Lov regions and the Loffregions can be independently controlled.

Abstract: A semiconductor device is constructed of at least one indium nitride or indium nitride alloy nanostructure on a substrate or other thing film layer. The method used to create the semiconductor device involves illuminating the substrate with a lateral intensity patterning of ultraviolet light in the presence of at least hydrazoic acid and a compound containing indium gas flows. Additionally, a semiconductor light-emitting/detecting modulating device composed of at least one indium nitride or indium nitride alloy nanostructure. The method used to create the semiconductor light-emitting/detecting modulating device involves embedding at least one nanostructure in the interior layer of the device. Further, a monolithic photovoltaic-photoelectrochemical device where one layer is composed of an indium nitride or indium nitride alloy film or nanostructure.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract: An active matrix substrate includes a substrate composed of resin, and a polysilicon thin film diode formed on the substrate. The polysilicon thin film diode may be a lateral diode centrally having a region into which impurity is doped. As an alternative, the polysilicon thin film diode may be comprised of two lateral diodes electrically connected in parallel to each other and arranged in opposite directions.

Abstract: A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.

Abstract: A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

Abstract: The present invention relates to a plasma doping system capable of handling larger-diameter wafers and of introducing impurities to a shallow depth with a lower energy level. The plasma doping system includes a plasma generation chamber provided with a high-frequency power source and with antennas for generating a helicon plasma of a gas containing conduction type impurities. An impurity introduction chamber is provided with a substrate holding fixture. A plasma flow passage/shaping chamber provides a flow passage through which the helicon plasma flows from the plasma generation chamber to the impurity introduction chamber and has a magnetic field generator for generating a magnetic field to constrict the helicon plasma flowing therethrough.

Abstract: Provided with a laser diode and its fabricating method including the steps of: sequentially forming a first conductivity type clad layer, an active layer, a second conductivity type first clad layer, an etch stop layer, a second conductivity type second clad layer, a second conductivity type InGaP layer, and a second conductivity type GaAs layer, on a first conductivity type substrate; forming an insulating layer on the second conductivity type GaAs layer and patterning it, exposing a defined region of the second conductivity type GaAs layer; performing a reactive ion etching using the patterned insulating layer as a mask, etching the second conductivity type GaAs layer, the second conductivity type InGaP layer, and the second conductivity type second clad layer to a specified depth and remaining part of the second conductivity type second clad layer; forming a photoresist on the whole surface including the insulating layer and patterning it, exposing the residual second conductivity type second clad layer; p

Abstract: There is provided a method for manufacturing a thin film transistor. The present invention can reduce the number of process steps for manufacturing a thin film transistor, and also can lower contact resistance between layers. The manufacturing method deposits a buffer layer and an active layer on a substrate. The active layer is crystalized and patterned. Then, an insulating layer is deposited on an upper surface of the active layer and patterned to form a gate electrode on an upper surface of the insulating layer by a photolithography process using a photoresist layer. The photoresist layer covering the gate electrode is reflowed by heating and covers the edges of the gate electrode. A contact layer is formed by doping in high concentration at both edges of the active layer by plasma ion-injecting using the reflowed photoresist layer as a mask. After removing the photoresist layer, an LDD region is formed at the active layer by ion-injecting in low concentration.

Abstract: An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.

Abstract: A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate.

Abstract: Drain and source extensions that are abrupt and shallow and that have high concentration of dopant are fabricated for a field effect transistor, using a laser thermal process. A drain amorphous region is formed by implanting a neutral species into a drain region of the field effect transistor at an angle directed toward a gate of the field effect transistor such that the drain amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A source amorphous region is formed by implanting the neutral species into a source region of the field effect transistor at an angle directed toward the gate of the field effect transistor such that the source amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A drain and source dopant is implanted into the drain and source amorphous regions at an angle directed toward the gate of the field effect transistor.

Abstract: In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.

Abstract: Thin-film switching elements (20,21) of a display device or the like include a first electrode (22,23) on a substrate (11) and a layer of switching material (24,25) on the first electrode. These switching elements may be semiconductor PIN or Schottky diodes, or MIMs, or TFTs. The switching material is typically .alpha.-Si:H in the case of the semiconductor diodes and TFTs, and tantalum oxide or silicon nitride in the case of the MIMs. An auxiliary layer (28,29) of insulating material is provided between the first electrode (22,23) and the layer of switching material (24,25), leaving an edge (30,31) of the first electrode uncovered, so that the layer of switching material is connected to this edge only. The switching elements with this construction can be patterned using an inexpensive proximity printer, and have a low capacitance value, so counter-acting kickback and crosstalk which can occur in a switching matrix, e.g in the display of television pictures.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: A method for n-doping a material layer with antimony, comprising ion implanting antimony from an antimony precursor composition including a compound of the formula SbX.sub.n ((CH.sub.2).sub.y SiR.sub.3).sub.n-3, wherein: n is an integer having a value of 1 or 2; y is an integer having a value of from 1 to 3 inclusive; each R is independently selected from C.sub.1 -C.sub.4 alkyl; and each X is independently selected from halo substituents. The antimony precursor composition may further include a fluorine-containing auxiliary gas, to effect in situ cleaning of the ionization chamber during ion implantation.

Abstract: A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate.

Abstract: After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.

Abstract: A semiconductor device formed on an insulating substrate of the present invention includes: a gate wiring provided on the insulating substrate; a first insulating film provided so as to cover the gate wiring; an upper electrode formed so as to face the gate wiring in such a manner that the first insulating film is interposed therebetween; a second insulating film provided so as to cover the upper electrode; and another electrode formed on the second insulating film, wherein the upper electrode is electrically connected to the another electrode via a contact hole formed through the second insulating film, a storage capacitor is formed of a structure including the upper electrode, the first insulating film, and the gate wiring opposing the upper electrode through the first insulating film, the upper electrode and the gate wiring have substantially the same width.