Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.

Abstract: A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Abstract: A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.

Abstract: Fabrication of a Group III-nitride transistor device can include implanting dopant ions into a stacked Group III-nitride channel layer and Group III-nitride barrier layer to form source/drain regions therein with a channel region therebetween. The channel layer has a lower bandgap energy than the barrier layer along a heterojunction interface between the channel layer and the barrier layer. The source/drain regions have a lower defect centers energy than the channel region. The source/drain regions and the channel region are exposed to a laser beam with a wavelength having a photon energy that is less than the bandgap energy of the channel region and higher than the defect centers energy of the source/drain regions to locally heat the source/drain regions to a temperature that anneals the source/drain regions.

Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Abstract: Embodiments of semiconductor devices and methods for fabricating the semiconductor devices are provided. The method includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor. The gate electrode structure is disposed on a channel region of a first silicon-germanium alloy. A strain-inducing silicon-germanium alloy is formed in the cavity and in contact with the first silicon-germanium alloy. The strain-inducing silicon-germanium alloy includes carbon and has a composition different from the first silicon-germanium alloy.

Abstract: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: A flexible electret transducer assembly including an electrical backplate and a membrane made of an electret material is disclosed. A plurality of spacers is formed on a surface of the electrical backplate in a longitudinal or latitudinal direction, and the spacers are used for supporting a vibrating room of the membrane. A working area of the membrane is formed between adjacent spacers, and in each of the working area, the space between the electrical backplate and the membrane is smaller than that in a conventional electrostatic speaker. The spacers between the electrical backplate and the membrane are mass produced through a stamping process. Thereby, an accurate space between the electrical backplate and the membrane can be maintained and accordingly the audio quality can be improved. In addition, a speaker including the flexible electret transducer assembly and a method for fabricating the flexible electret transducer assembly are also disclosed.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

Abstract: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

Abstract: A method for fabricating a semiconductor device includes: forming a channel layer; forming an electron supply layer on the channel layer; forming a cap layer made of gallium nitride on the electron supply layer; and performing an oxygen plasma treatment to an upper surface of the cap layer at a power density of 0.0125˜0.15 W/cm2.

Abstract: A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided.

Abstract: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.

Abstract: A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

Abstract: The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.

Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.

Abstract: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

Abstract: A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.

Abstract: An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the first device and the die attach paddle with an encapsulation having a top surface; and etching the die attach paddle leaving a recess in the top surface of the encapsulation.

Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.

Abstract: According to one embodiment, a semiconductor structure including an equipotential field modulation body comprises a trench surrounding an active region of a group III-V power device fabricated in the semiconductor structure, and the equipotential field modulation body formed in the trench and extending over a portion of the active region. The equipotential field modulation body is electrically coupled to a terminal of the group III-V power device. In one embodiment, a method for fabricating a semiconductor structure including an equipotential field modulation body comprises fabricating a trench surrounding an active region of the semiconductor structure, forming the equipotential field modulation body in the trench, the equipotential field modulation body extending over a portion of the active region, and electrically coupling the equipotential field modulation body to a terminal of a group III-V power device fabricated in the active region.

Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).

Abstract: A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0?x<1, 0<y<1, 0<x+y<1); a first etch stop layer 105 disposed over the first electron-supplying layer 104 and containing indium aluminum nitride (InAlN); and a second electron-supplying layer 106 provided over the first etch stop layer 105 and containing InaAlbGa1-a-bN (0?a<1, 0<b<1, 0<a+b<1). A first recess 111, which extends through the second electron-supplying layer 106 and the first etch stop layer 105 and having a bottom surface constituted of a section of the first electron-supplying layer 104, is provided in the second electron-supplying layer 106 and the first etch stop layer 105. A gate electrode 109 covers the bottom surface of the first recess 111 and is disposed in the first recess 111.

Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.

Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer.

Abstract: A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1-yN (wherein 0<x?1, 0—y<1 and 0<x+y?1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.

Abstract: A method of fabricating an epitaxial compound semiconductor III-V wafer suitable for the subsequent fabrication of at least two different types of integrated active devices (such as an HBT and a FET) on such wafer by providing a substrate; growing a first epitaxial structure on the substrate; and growing a second epitaxial structure on the first epitaxial structure.

Abstract: A thin film photoelectric converter, especially an integrated thin film photoelectric converter having improved photoelectric conversion efficiency is provided by controlling an open-circuit voltage and a fill factor so as not be small in a thin film photoelectric converter including a crystalline silicon photoelectric conversion unit. The thin film photoelectric converter by the present invention has at least a transparent electrode film, a crystalline silicon photoelectric conversion unit, and a back electrode film formed sequentially on one principal surface of a transparent substrate, and the converter has a whitish discoloring area on a part of a surface of the converter after formation of the crystalline silicon photoelectric conversion unit. A percentage of dimensions of the whitish discoloring area preferably is not more than 5% of a dimension of the photoelectric conversion area.

Abstract: According to an exemplary embodiment, a PHEMT (pseudomorphic high electron mobility transistor) structure includes a conductive channel layer. The PHEMT structure further includes at least one doped layer situated over the conductive channel layer. The at least one doped layer can include a heavily doped layer situated over a lightly doped layer. The PHEMT structure further includes a recessed ohmic contact situated on the conductive channel layer, where the recessed ohmic contact is situated in a source/drain region of the PHEMT structure, and where the recessed ohmic contact extends below the at least one doped layer. According to this exemplary embodiment, the recessed ohmic contact is bonded to the conductive channel layer. The recessed ohmic contact is situated adjacent to the at least one doped layer. The PHEMT structure further includes a spacer layer situated between the at least one doped layer and the conductive channel layer.

Abstract: Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

Abstract: A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150° C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 ? thick AlN layer.

Abstract: A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.

Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from the source region and the gate region abutting the channel region. The channel region includes a channel layer having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer and applies a stress to the channel region along a boundary between the substrate layer and the channel layer.

Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.

Abstract: A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode.

Abstract: Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.

Abstract: A method and a multijunction solar device having a high band gap heterojunction middle solar cell are disclosed. In one embodiment, a triple-junction solar device includes bottom, middle, and top cells. The bottom cell has a germanium (Ge) substrate and a buffer layer, wherein the buffer layer is disposed over the Ge substrate. The middle cell contains a heterojunction structure, which further includes an emitter layer and a base layer that are disposed over the bottom cell. The top cell contains an emitter layer and a base layer disposed over the middle cell.

Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

Abstract: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure.