Abstract: A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls.

Abstract: A method of making a semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide is disclosed, in which the lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: A manufacturing method that is capable of easily manufacturing a semiconductor device exhibits high reliability with no decrease in field isolation voltage from overetching. A field oxide is formed on a silicon substrate by a LOCOS method and a silicon nitride layer is then formed on the field oxide. Polysilicon is deposited on the surface of the field oxide and on the surface of a silicon nitride layer. The polysilicon layer is deposited thicker than a thickness of the silicon nitride layer. The polysilicon layer deposited on the silicon nitride layer and on the field oxide is removed by a polishing CMP method or the like, whereby the surface of the silicon nitride layer is exposed. A structure having the polysilicon layer existing on only the surface of the field oxide is then obtained by removing the silicon nitride layer. The polysilicon layer functions as a protective layer for the field oxide, thereby preventing the field oxide layer from being etched during overetching.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs are provided on an SOI substrate. The thickness of a thin film on the substrate is varied to adjust the threshold voltage. The threshold voltage can be varied by roughly 240 mV. The thickness of the thin film can be adjusted through a LOCOS process.

Abstract: A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the field oxide layer within the scribe-line region to ensure the substrate and the conducting layer thereon are properly insulated. That prevents the leakage of the carriers generated by the Electro-optical effect to resolve the problem of an abnormally elevated output at the first pixel. In addition, a mask protects the dielectric layer on the scribe-line region from being etched, so the steep difference on the step height is improved to resolve the peeling of the photoresist. The field oxide layer under the dielectric layer covered by the dielectric layer then provides a better insulation.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer.

Abstract: In manufacturing a transistor, a doping mask is formed above a substrate. The doping mask is constructed, so that a first region of the substrate for serving as a source in the transistor and a second region of the substrate for serving as a drain in the transistor are substantially shielded. Once the doping mask is formed, ions are introduced into a region in the substrate that is to underlie the transistor's gate structure. The ions are introduced to establish the characteristics of the transistor, such as the transistor's threshold voltage and punch-through breakdown voltage. After the ions are introduced, a gate oxide is formed to overlie a portion of the substrate. The gate structure for the transistor is then formed to substantially overlie the region of the substrate in which the ions have been introduced. Once a gate is formed for the gate structure, a source and drain are formed in the substrate.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.

Abstract: The present invention proposes a method for forming vertically modulated wells in a semiconductor substrate. The method can include the steps as follows. At first, isolation regions are formed over the substrate. A pad layer is then formed over the substrate and a photoresist layer is formed over the pad layer. Then, p-well regions are defined by removing portions of the photoresist layer. Next, first p-wells are formed in the substrate under the p-well regions. After forming a masking layer over the p-well regions, the photoresist layer is removed. A first thermal process is then performed. Second p-wells are formed in the substrate at a level below the first p-wells. Next, n-wells are formed in the substrate under regions uncovered by the masking layer and above the second p-wells. The masking layer and the pad layer are then removed. Finally, a second thermal process is performed to finish the formation of vertically modulated wells.

Abstract: A method for forming an isolation region of a semiconductor device includes the steps of forming first and second insulating layers on a substrate, removing the second insulating layer over an isolation region, forming an oxide layer by oxidizing the first insulating layer over the isolation region, forming sidewall spacers at sides of the second insulating layer and over the isolation region, forming a trench by etching the oxide layer and the substrate at the isolation region, removing the sidewall spacers, forming a third insulating layer on the substrate in the trench, and forming an isolation layer in the trench.

Abstract: A method for integrating a high-voltage device and a low-voltage device. A substrate has a high-voltage device region, a low-voltage device region and a scribe region, wherein a patterned insulating layer is formed on the substrate in the high-voltage device region and the scribe region. A grade region is formed in the substrate exposed by the patterned insulating layer in the high-voltage device region. A plurality of protuberances is formed on the substrate exposed by the patterned insulating layer in the high-voltage device region and in the scribe region. The patterned insulating layer and the protuberances are removed to form recesses at locations of the protuberances. A first gate structure and a second gate structure are respectively formed on the substrate between the grade region in the high-voltage device region and on the substrate in the low-voltage device region while using the recesses as alignment marks.

Abstract: The method of the invention starts with forming a mask on a blank wafer, wherein the mask contains a number of openings that expose a portion of the wafer. By performing a wet oxidation process, field oxide is formed on the exposed surface of the wafer. The wafer surface is then become ragged after the mask and the field oxide are removed. In order to further increase the surface area of a dummy wafer, an etching process is performed on the ragged surface after a hemispherical grained layer is formed on the ragged surface.

Abstract: A method for fabricating a field device transistor includes forming a gate oxide layer of the field device transistor by performing a thermal oxidation process. By properly controlling the thickness of the gate oxide layer, the threshold voltage of the field device transistor can be suppressed in under 5 volts to provide sufficient protection for the internal circuit. The method of the invention includes forming a gate oxide layer of a field device transistor by performing a thermal oxidation process instead of a field oxide layer in order to obtain a better control on the thickness of the gate oxide layer.

Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.

Abstract: The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication.To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

Abstract: Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well.

Abstract: In a trench isolation structure having active regions at a main surface of a silicon substrate isolated by providing a gate electrode on an insulation film formed in a trench with a gate oxide film thereunder, the insulation film has a vertical cross section configuration wherein the carrier concentration of the active region at the proximity of the upper edge corner of the trench becomes lower than the carrier concentration at the center of the active region in a state where a predetermined bias voltage is applied to the gate electrode. According to this structure, electric field concentration at the edge of the trench isolation can be relaxed and generation of an inverse narrow channel effect suppressed. Therefore, the subthreshold characteristics can be improved.

Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Abstract: A technique for reducing active area encroachment (birdsbeak) by using a polysilicon hard mask combined with both wet and dry etch for the isolation nitride. This process forms a thinner layer of nitride adjacent the openings for oxide growth, which reduces stress at the silicon/nitride interface. The advantages include control over birdsbeak, reliable gate oxide quality, low junction leakage current, an improved active area, improved isolation, low peripheral junction leakage, and higher field transistor threshold voltage.

Abstract: A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas.

Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

Abstract: Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self-aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.

Abstract: A method of manufacturing a semiconductor device comprising the steps of masking element areas of a silicon substrate of a first conductivity type with a masking layer; forming a field oxide film on field areas of the silicon substrate which are not protected by said masking layer to define separate element areas; introducing first impurities of the first conductivity type into the field oxide film; removing the masking layer and introducing second impurities of a second conductivity type opposite the first conductivity type into the field oxide film and into the element area to form an impurity diffusion layer; forming a refractory metal film over an area extending from the impurity diffusion layer to the field area; and heat treating to form a refractory metal silicide on the surface of the impurity diffusion layer.

Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.

Abstract: A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer.

Abstract: An isolation region is formed in a semiconductor substrate for separating a functional region and a ESD protective region. A gate structure and lightly doped active region is formed. An insulator layer is formed and a portion of the layer is removed for a spacer. A doping is performed using the spacer and gate as a mask. An exposed region located aside the gate is defined in the ESD protective region. A covering layer is formed and a first thermal annealing is performed. A junction diode is also formed. A MOS transistor with self-aligned silicide contacts with an ESD protection improvement is formed. The MOS transistor for the ESD protection in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both kind of transistors in a functional region. The ESD protection effect is raised with a low breakdown junction diode. A lightly doped drain (LDD) structure and an ultra-shallow junction are embedded in the devices.

Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.

Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide.

Abstract: The present invention provides a fabrication process for fabricating an integrated circuit substrate structure having LOCOS isolation areas formed such that oxidation encroachment at an active surface region patterned on the substrate is less than 0.1 .mu.m. The fabrication process includes various process steps for forming a 0.75 .mu.m. to 1.0 .mu.m layer of silicon dioxide (SiO.sub.2) over thin layers of silicon dioxide (0.01 .mu.m. to 0.05 .mu.m) and silicon nitride (0.05 .mu.m. to 0.10 .mu.m) over a surface region of the substrate to form a protective stack/passivation layers over a surface region of the silicon substrate. The protected substrate surface region is useable for fabricating a microelectronic circuit device, such as a MOS transistor, or a flash memory device. Adjacent the protective stack, a silicon nitride spacer region is formed to effectively widen the protected substrate surface region.

Abstract: A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

Abstract: The invention provides a trench isolation structure comprising a semiconductor region, a first insulation film formed on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator being formed which resides not only on the first insulation film but also within the trench groove so that the inter-layer insulator fills up the trench groove.The present invention still further provides a method for forming a trench isolation in a semiconductor region. The method comprises the following steps. A first insulation film is formed on a top surface of a semiconductor region.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: The present invention is a blanket well counter doping process for high speed and low power MOSFETs. An N-well region and a P-well region are in a substrate and a pad silicon oxide layer is on the substrate. A silicon nitride pattern is formed on the pad oxide layer to define active regions of the N-well and P-well region, a field oxide region is formed by using the silicon nitride as a mask. Afterward, an N-type ion implantation is implemented for anti-punchthrough region of the N-well region. A blanket P-type ion implantation is performed for N-well counter doping and P-well doping. A P-type low-energy and low-dosage ions is then implanted into the substrate for the threshold voltage adjustment. The last implantation stage is N-type and low dose to form a P-well counter doping region and an N-well doping region.

Abstract: A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the silicon substrate.

Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: The invention relates to a process for making a transistor with self-aligned contact points and comprises the following steps: formation of multiple layers on a substrate (100) and etching of the multiple layers using a first mask, but preserving a column of the multiple layer; formation of lateral spacers on the sides of the column and implantation of impurities; local oxidation of the silicon substrate within the implanted region and elimination of the lateral spacers; deposit of a layer of insulating material (130) surrounding the column; etching of the column in accordance with a second mask to form a grid structure (140) with second sides, and exposing third sides delimiting the active region; formation of self-aligned insulating spacers (142, 143) on the second and third sides, and implantation of the source and drain (150, 152); formation of contact points (160, 162).

Abstract: In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.

Abstract: Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer.

Abstract: A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during the etching step used to form the oxide spacers on the sides of the polysilicon gates. The retained spacer oxide portions increase the total oxide thickness in the field area to effectively block the ion implantation used to form the heavily doped portions of the source and drain regions. This enables use, in the initial fabrication steps, of a grown field oxide of reduced thickness and advantageously a correspondingly reduced width so as to reduce the chip space allocated to the field oxide.

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.