Abstract: Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate dielectric material. The first gate material in the second region is implanted with a material different than the first metal to form a second gate material comprising a second metal. The work function of the CMOS device is set by the material selection of the gate materials.

Abstract: Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.

Abstract: A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation. Consequently, with a semiconductor device of the CMOS structure, it is possible to prevent unwanted creeping of silicide that occurs often in the shallow junction region depending on a concentration of an impurity having a low diffusion coefficient as represented by arsenic. Further, not only can the resistance in the shallow junction region be lowered, but also an amount of overlaps can be optimized in each transistor.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

Abstract: Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800).

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate, removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region, selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region, removing the second insulation film, polishing the second semiconductor layer in the third region using the second insulation film in the second region as a stopper after the second semiconductor layer is formed, and forming semiconductor elements on the first semiconductor layer and the second semiconductor layer after the second insulation film is removed.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: A method of manufacturing a transistor of a semiconductor device is provided. The method includes forming an N type gate pattern and a P type gate pattern on a substrate, implanting N type impurities into an N type transistor area, forming an insulation layer on the substrate including the N type gate pattern, forming a first spacer on a sidewall of the P type gate pattern by partially etching the insulation layer in a P type transistor area, and implanting P type impurities into the P type gate pattern and into the P type transistor area, thereby forming a CMOS transistor on the substrate. Thus, damage to the substrate and the transistor is prevented, thereby improving electrical characteristics of the transistor.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate.

Abstract: A semiconductor device in which electro-thermal conversion elements and switching devices for flowing currents through the elements are integrated on a first conductive type semiconductor substrate. The switching devices are insulated gate type field effect transistors having a second conductive type first semiconductor region on one principal surface of the semiconductor substrate; a first conductive type second semiconductor region for supplying a channel region and for adjoining the first semiconductor region; a second conductive type source region on the surface of the second semiconductor region; a second conductive type drain region on the surface of the first semiconductor region; and gate electrodes on the channel region with a gate insulator film between them. The second semiconductor region is formed by a semiconductor having an impurity concentration higher than that of the first semiconductor region, and is disposed between two adjacent drain regions, separating them in a traverse direction.

Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

Abstract: A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.

Abstract: In a method for manufacturing a semiconductor device, a gate insulating film and a gate electrode are first formed on a substrate. Next, Ge ions, Si ions, or the like are implanted to make the surface of the substrate amorphous, using the gate electrode as a mask. Thereafter, impurities such as B ions or the like, for forming a doped region, are implanted into the amorphous area of the substrate, using the gate electrode as a mask. Furthermore, the doped region is irradiated with visible light for a short period of time.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, and then forming a gate insulating layer on the semiconductor substrate. A lower gate electrode layer and a cap gate layer are formed on the gate insulating layer. The lower gate electrode layer and the cap gate layer are patterned to form a gate electrode structure. An LDD region is formed on the semiconductor substrate. An oxide layer is formed on the gate electrode structure and the semiconductor substrate. A thickness of the oxide layer is greater than a thickness of the gate insulating layer. Next, a nitride layer is formed on the oxide layer. Finally, the oxide layer and the nitride layer are etched to form a nitride sidewall spacer on the gate electrode structure through the oxide layer.

Abstract: A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive—in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.

Abstract: A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is formed on the substrate. The second patterned photoresist layer, the cured remaining first patterned photoresist layer and the gate form two openings alongside the gate structure. Finally, via the openings, two consecutive ion implantation processes are performed to form a double diffuse drain (DDD) structure.

Abstract: A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

Abstract: A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.

Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Abstract: A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.

Abstract: A manufacturing method for a bipolar gate CMOS semiconductor device is provided that eliminates a masking process for P-type polycrystalline silicon. An N-type polycrystalline silicon region is selectively formed in polycrystalline silicon constituting a gate electrode through predeposition using an insulating film as a mask, after which the insulating film is removed to implant P-type impurity ions into the entire surface to form a P-type polycrystalline silicon region.

Abstract: A gate structure (4), an LDD region (6) and a sidewall (7) are provided in this order. Arsenic ions (8) are thereafter implanted into the upper surface of a silicon substrate (1) by tilted implantation. The next step is annealing for forming an MDD region (9) in the upper surface of the silicon substrate (1). The MDD region (9) and the gate structure (4) do not overlap one another in plan view. Further, the MDD region (9) formed into a depth shallower than that of the LDD region (6) is higher in concentration than the LDD region (6). Thereafter a source/drain region (11) higher in concentration than the MDD region (9) is provided by vertical implantation into a depth greater than that of the LDD region (6).

Abstract: In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising: a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site; b) forming an undoped polysilicon layer over the gate oxide layer; c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer; d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions; e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; and f) affecting cooling after laser annealing to convert a-Si into p

Abstract: A method for manufacturing a semiconductor device is disclosed, in which characteristics of the semiconductor device and an operation speed are improved. In forming sidewall spacers at both sides of a gate electrode, a semiconductor substrates is partially removed at both sides of the sidewall spacer by controlling an etch gas, and then a process for forming a silicide layer is performed, thereby increasing a distance between the silicide layer and a channel. Accordingly, it is possible to decrease a resistance material between the silicide layer and the channel region.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: An optical bench on which an optical component is mounted comprises an Si substrate made of a silicon wafer, a groove disposed on the Si substrate and designed to mount the optical component thereon, and a metal thin-film wiring for driving the optical component or a driver component. The metal thin-film wiring is formed in an electroless plating process before a groove manufacturing process which forms the groove by micromachining by means of wet processing.

Abstract: A dividing apparatus for dividing a plate-like workpiece, which is put on the top surface of a protective tape affixed to an annular frame and has reduced strength along dividing lines, along the dividing lines, comprising:

Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.

Abstract: An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract: A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.

Abstract: There is provided a semiconductor device having such a protective film that selectively covers the surface of embedded interconnects and can effectively prevent both of the oxidation and the thermal diffusion of the interconnects. A method for manufacturing such a semiconductor device is also provided. The semiconductor device includes: a semiconductor substrate having an embedded interconnect structure in which the embedded interconnects have an exposed surface; and a protective film composed of a multi-layer laminated film formed selectively on the exposed surface of interconnects. The multi-layer laminated film preferably includes an oxidation-preventing layer, composed of e.g. a Ni or Ni alloy layer, for preventing oxidation of the interconnects, and a thermal diffusion-preventing layer, composed of e.g. a Co or Co alloy layer, for preventing thermal diffusion of the interconnects.

Abstract: Integrated circuit capacitor electrodes include a first conductive ring on a face of an integrated circuit substrate. A second conductive ring is provided on the first conductive ring opposite the substrate. A third conductive ring also is provided on the first conductive ring opposite the substrate. The third ring is located at least partially within the second ring. A conductive layer electrically connects the first, second and third rings. To form the electrodes, a first conductive layer is conformally deposited in the areas in which the electrodes will be formed and on a mold oxide layer. A first buffer dielectric layer is deposited on the first conductive layer. The first buffer dielectric layer and the first conductive layer are etched to separate nodes of the first conductive layer. Recessed portions are formed by further etching the first conductive layer.

Abstract: A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on-glass layer may be deposited over the non-uniform passivation layer prior to planarization. Once a uniform, flat first passivation layer is achieved over the final metal, a second passivation layer, a color filter array, or a lens forming layer with uniform thickness is formed over the first passivation layer. The passivation layers can be oxide, nitride, a combination of oxide and nitride, or other suitable materials. The color filter array layer may also undergo a planarization process prior to formation of the lens forming layer. The present invention is also applicable to other devices.

Abstract: A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

Abstract: An object of the invention is to improve the position, shape, and size of a bump in order to realize highly reliable flip-chip mounting. In the case of the semiconductor device of this embodiment, a stacked bump 14 is provided on electrode pad 12 created on the main surface of semiconductor chip 10. That is, said bump 14 comprises columnar pedestal part 14a and columnar tail part 14b having a smaller diameter than that of pedestal part 14a. Peak plane of tail part 14b (peak plane of the bump) and the top surface of pedestal part 14a are both flat. Said bump 14 is created through gold plating, for example, using a resist (photolithography) technology and a plating technology.

Abstract: A semiconductor device having CMOS circuits formed on a glass substrate. The CMOS circuits are composed of TFTs. Lightly doped regions are formed only in the N-channel TFTs. When P-channel TFTs are formed, the conductivity type of the lightly doped regions is converted by a boron ion implant. Each CMOS circuit consists of an N-channel TFT having the lightly doped regions and a P-channel TFT having no lightly doped regions.

Abstract: A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Abstract: A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.

Abstract: The assembly comprises a circuit (3) for detecting errors in data supplied by at least one of the blocks of the assembly. When an error has been detected, the assembly is decontaminated by means of at least one circuit for backup and reconstitution of past states of a latch associated to a block. The backup and reconstitution circuit comprises a multiplexer (6) and a FIFO buffer register (5). The multiplexer comprises a first input directly connected to the output of the latch (2a) and a second input connected to this output via the buffer register. A control circuit (4) controls the buffer register and the multiplexer so as to activate the buffer register writing function and connect the output of the multiplexer to its first input at each cycle, during a normal operating phase, and the read enable the buffer register and connect the multiplexer output to its second input during predetermined cycles of a decontamination phase.

Abstract: An information processing apparatus or a semiconductor memory according to the present invention periodically refreshes a high-speed nonvolatile memory cell having spontaneous data storing capability at the time of nonuse of the apparatus (or at the time of standby of the memory) by refresh control element. Thus, a combination of the spontaneous data retaining capability of the nonvolatile memory cell, the periodic refresh at the time of nonuse, and intermittent power supply by turning on/off switch means makes it possible to retain data reliably while minimizing power consumption at the time of standby. Thereby a memory system that can retain data reliably with minimum power consumption and enable high-speed access can be realized.

Abstract: A method of forming organic spacers using an N2 plasma or N2 containing plasma anisotropic etchant, and using such organic spacers for forming features on a semiconductor structure such as vias having a smaller dimension than can be defined by lithographic techniques Other features formed according to the teachings of this invention include Source/Drain (S/D) areas, LDD/extension areas and graded junctions with larger S/D silicide/contact areas. The process for forming the organic spacers comprises conformally coating a patterned semiconductor structure with an organic material such as, for example, an antireflective coating. The coated structure is then anisotropically etched with N2 plasma or N2 containing plasma which forms the organic spacers.

Abstract: Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.