Abstract: A manufacturing method of a semiconductor super-junction device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer and a second insulating layer as a mask to form a second groove in the n-type substrate. A gate structure is formed in the second groove.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: The embodiments herein relate to field-effect transistors (FETs) with a gate structure in a dual-depth trench isolation structure and methods of forming the same. The FET includes a substrate having an upper surface, a trench isolation structure, and a gate structure adjacent to the trench isolation structure. The trench isolation structure has a first portion having a lower surface and a second portion having a lower surface in the substrate; the lower surface of the first portion is above the lower surface of the second portion.

Abstract: A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a gate dielectric layer on the barrier layer; forming a work function metal layer on the gate dielectric layer; patterning the work function metal layer and the gate dielectric layer; forming a gate electrode on the work function metal layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A semiconductor device includes a semiconductor part, a first electrode and control electrodes at the front side of the semiconductor part. The semiconductor part includes first to fourth layers, first and third layers being of a first conductivity type, second and fourth layers being of a second conductivity type. The control electrodes are provided in a plurality of trenches, respectively. The control electrodes include a first control electrode, and a second control electrode next to the first control electrode. The second layer is provided between the first layer and the first electrode. The third and fourth layers are provided between the second layer and the first electrode. The semiconductor part further includes a first region partially provided between the first and second layers. The first region is provided between the first and third layers, the first region including a material having a lower thermal conductivity than the first layer.

Abstract: The present disclosure discloses a semiconductor device and a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes following steps: providing a semiconductor substrate, and forming active regions and trench isolation structures in the semiconductor substrate, wherein the trench isolation structures are located between the active regions; forming first grooves in the active regions; filling the first grooves to form inversion polysilicon layers, the inversion polysilicon layers being inversely doped with the active regions; forming second grooves, the second grooves running through the polysilicon layers and a part of the semiconductor substrate, and reserving parts of the inversion polysilicon layers located on side faces of the second grooves; and, forming buried word line structures in the second grooves.

Abstract: Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A multilayer composite film is on the P-type layer, the multilayer composite film comprising: a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by sidewalls in the dielectric layer and the first portion of the current spreading layer; and a P-contact layer in the via opening on the first portion of the current spreading layer, the sidewalls in the dielectric layer, and on at least a portion of the dielectric layer.

Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.

Abstract: A semiconductor device for reducing a switching loss includes a drain metal. A silicon substrate of a first conductive type is provided on the drain metal. An epitaxial layer of the first conductive type is provided on the silicon substrate of the first conductive type. A pillar of the first conductive type and a pillar of a second conductive type are arranged in the epitaxial layer of the first conductive type. A body region of the second conductive type is provided on a surface of each pillar. A heavily doped source region of the first conductive type and a heavily doped source region of the second conductive type are arranged in the body region of the second conductive type. A gate trench is formed in the pillar of the first conductive type. Discrete gate polycrystalline silicon is provided in the gate trench.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Abstract: A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 ?m from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×1013/cm3. In the deep region of the first-conductivity-type semiconductor layer, a maximum value of a concentration of boron is less than 1.0×1014/cm3.

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.

Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

Abstract: A semiconductor device according to an embodiment includes first and second electrodes, a gate electrode, first to third semiconductor regions, and first and second insulating parts. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The gate electrode is located in the first insulating part. The gate electrode faces the second semiconductor region. The second insulating part is located on the third semiconductor region. The second insulating part is not overlapping the gate electrode. The second insulating part has tensile stress. The second electrode is located on the second insulating part and electrically connected with the third semiconductor region.

Abstract: Methods for forming defect-free gap fill materials comprising germanium oxide are disclosed. In some embodiments, the gap fill material is deposited by exposing a substrate surface to a germane precursor and an oxidant simultaneously. The germane precursor may be flowed intermittently. The substrate may also be exposed to a second oxidant to increase the relative concentration of oxygen within the gap fill material.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

Abstract: The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.

Abstract: A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.

Abstract: A power semiconductor device includes: a semiconductor body with a drift region; a plurality of trenches, wherein two adjacent trenches laterally confine a mesa of the semiconductor body. Each trench extends along a vertical direction and includes a trench electrode, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length amounting to at least five times the trench width. The device further includes: a semiconductor body region of a second conductivity type in the mesa; a source region in the mesa; an insulation layer above and/or on the source region; a contact plug that extends at least from an upper surface of the insulation layer along the vertical direction so as to contact both the source region and the semiconductor body region.

Abstract: A semiconductor device includes a semiconductor part, an first electrode, a control electrode and second electrodes. The control electrode and the second electrodes are provided between the semiconductor part and the first electrode, and provided inside trenches, respectively. The second electrodes include first to third ones. The first and second ones of the second electrodes are adjacent to each other with a portion of the semiconductor part interposed. The second electrodes each are electrically isolated from the semiconductor part by a insulating film including first and second insulating portions adjacent to each other. The first insulating portion has a first thickness. The second insulating portion has a second thickness thinner than the first thickness. The first insulating portion is provided between the first and second ones of the second electrodes. The second insulating portion is provided between the first and third ones of the second electrodes.

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

Abstract: A shield gate trench power device, wherein a shield dielectric layer is formed by stacking a thermal oxide layer and a CVD dielectric layer on the inner side surface of a gate trench; a gap region formed by means of filling with the shield dielectric layer is filled with source polysilicon; a top trench is formed on two sides of the source polysilicon by etching a portion of the shield dielectric layer close to the side surface of the gate trench, and the entire top trench is located in the thermal oxide layer; the top trench is filled with a polysilicon gate. A method for manufacturing a shield gate trench power device. The uniformity of the thickness of the shield dielectric layer on the sidewall and bottom of the gate trench can be improved.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, and a gate electrode is formed over the substrate. The gate electrode has a sidewall, and the gate electrode is laterally positioned between the first source/drain region and the second source/drain region. A buffer dielectric layer is formed that includes a first dielectric layer having a first portion positioned between the substrate and the gate electrode. The dielectric layer also has a second portion positioned on the substrate laterally between the sidewall of the gate electrode and the first source/drain region. The first portion of the dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness that is less than the first thickness.