Abstract: Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126).

Abstract: The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.

Abstract: A semiconductor read-only memory (ROM) device having a silicon-on-insulator (SOI) structure and a method for fabricating the same are provided. The SOI structure permits isolation of the source/drain regions from the underlying substrate, thereby preventing leakage current therebetween. The ROM device of the present invention is smaller than conventional ROM devices, and thus provides increased integration without generating leakage paths due to misalignment of the contact windows used to form metal interconnects. The ROM device includes a plurality of parallel gate regions and a grid-like polysilicon conductive layer. The grid-like structure includes a plurality of substantially parallel source/drain regions on both sides of the gate regions, and a plurality of substantially parallel channel regions crossing the source/drain regions and the gate regions at right angles. Select locations of the channel regions are impurity-doped, causing the associated memory cells to be set to a permanently-OFF state.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well, forming a field oxide in the overlapping portion of the first and second conductive wells forming a first gate over the first conductive well and a second gate over the second conductive well, masking the first conductive well and implanting second conductive impurities on the second conductive well and masking the second conductive well and implanting first conductive impurities on the first conductive well.

Abstract: A semiconductor integrated circuit device includes a first conductor formed on a main surface of a semiconductor substrate with an insulating film therebetween, and a second conductor formed with an insulating film therebetween so as to be placed near one side of the first conductor and to have its one end extended over a top surface of the one side of the first conductor. The semiconductor integrated circuit device further includes an impurity diffusion layer at the main surface of the semiconductor substrate under a region where first and second conductors are close to each other. In accordance with this structure, higher degree of integration of a memory cell can be readily achieved by a relatively simple manufacturing process.

Abstract: A self-aligned silicide process for the formation of a mask ROM includes forming a self-aligned silicide layer over the bit lines and the word lines to lower the resistance of the bit lines and word lines in the mask ROM.

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

Abstract: A method of forming a multi-stage ROM which replaces the multiple code implant. A gate oxide layer, a first polysilicon layer, an oxide layer, a second polysilicon layer and a silicon nitride layer are formed over a substrate in succession. Then, the silicon nitride layer, the second polysilicon layer, the oxide layer, the first polysilicon layer and the gate oxide layer are patterned at the same time so that a number of double-layer polysilicon lines remain. An implantation is performed on an exposed region to form a number of source/drain regions which serve as bit lines. The double-layer polysilicon lines are patterned to form a number of gates, wherein each of the gates combines with the adjacent source/drain regions to form four memory cells. Two coding processes are performed to accomplish the process of manufacturing a multi-stage ROM.

Abstract: A method of making multi-level ROM devices in which the gate width controls the threshold voltage setting of each memory unit, instead of the conventional method of setting the threshold voltage through the implantation of ions into the channel region of a memory unit. The memory units include memory units having their word line polysilicon layer completely removed, which are units in an OFF state. Memory units having part of the word line polysilicon layer removed are units with a higher threshold voltage, while memory units having the word line polysilicon layer left untouched are memory units with a lower threshold voltage.

Abstract: A multi-stage ROM device capable of storing multi-stage data and allowing high packing density for a ROM chip thus fabricated and a process for fabricating such a multi-stage ROM device. In the ROM device, the intersection between a first bit line and a word line is formed with a diode having a threshold voltage controlled at about 0.7 V, and the intersection between another bit line and word line is formed with a bipolar transistor with a threshold voltage controlled at about 3 V-5 V. The other intersections are each formed with a permanently-OFF transistor. By using these different types of memory cells, the ROM device is capable of storing multi-stage data.