Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region.

Abstract: A method for differentiating integrated circuits implementing identical functions by storage of a binary code in a non-volatile storage element provided in each circuit, including providing, for each circuit of a same reticle, a selective implantation of dopants of its storage element which is different from the selective implantations of dopants of the storage elements of the other circuits.

Abstract: In a method for forming short-channel transistors, the method comprising the steps of: forming a first oxide layer and a sacrificial layer one after another on a semiconductor substrate and etching the sacrificial layer, thus forming a residual sacrificial layer pattern; conducting an ion implantation using the residual sacrificial layer pattern as a mask, thus forming an LDD ion-implant layer in the semiconductor substrate; forming the first spacers on both side walls of the residual sacrificial layer pattern; conducting an ion implantation using the residual sacrificial layer pattern and the first spacers as a mask, thus forming a source/drain ion-implant layer under the LDD ion-implant layer; forming a nitride layer and a second oxide layer one after another on the whole surface of the former resultant object and conducting an annealing treatment, thus forming source/drain regions; conducting chemical-mechanical polishing (CMP) processes to the extent that an upper surface of the residual sacrificial layer

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Abstract: The present invention provides a thin-film transistor (TFT) and its production method which enables an arrangement restraining bipolar transistor type behavior, in order to stabilize saturation current and to provide a TFT that can improve reliability. The TFT includes a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite this source region are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by introducing impurities, such as inert gases, metals, Group III elements, Group IV elements and Group V elements after a crystallization process is carried out on a semiconductor film 100.

Abstract: A method of forming a specialized channel region removes a sacrificial gate material and provides a semiconductor implant though the recess associated with the remove sacrificial gate material. The process can be utilized to form a silicon germanium layer in the channel region having a sharp profile in the vertical direction. Further, the silicon germanium layer can be ultra-thin. The silicon germanium channel region has increased charge mobility with respect to conventional channel regions.

Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

Abstract: The nonvolatile semiconductor memory device comprises a semiconductor substrate 10 with a trench 16 formed in the surface thereof, an impurity diffused region 24 formed in the surface of the semiconductor substrate 10 other than the region where the trench 16 is formed, an impurity diffused region 26 formed in the semiconductor substrate 10 at the bottom of the trench 16 and having a width smaller than that of the trench 16, a charge storage layer 28 of an insulating layer formed on the inside surface of the trench 16, and a conducting layer 36 formed on the charge storage layer 28 between the impurity diffused region 24 and the impurity diffused region 26. Whereby the punch-through between the impurity diffused region 24 and the impurity diffused region 26 can be effectively prevented, and resultantly writing can be efficiently performed.

Abstract: A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

Abstract: A gate insulating film is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed. An ONO film is formed on the side wall of the gate electrode and on the surface of the semiconductor substrate on both sides of the gate electrode, conformable to the side wall and the surface. A silicon nitride film of the ONO film traps carriers. A conductive side wall spacer faces the side wall of the gate electrode and the surface of the semiconductor substrate via the ONO film. A conductive connection member electrically connects the side wall spacer and gate electrode. Source and drain regions are formed in the surface layer of the semiconductor substrate in areas sandwiching the gate electrode. A semiconductor device is provided which can store data of two bits in one memory cell and can be driven at a low voltage.

Abstract: A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is formed on an upper surface of the gate electrode and on an upper surface of a substrate on which source and drain regions are formed, thereby providing a contact hole self-aligned between the gate electrodes. Also, an ion implantation process is performed on the entire active region after the contact hole is filled with metal such as tungsten, and an impurity region is formed only on a lower portion of the gate electrode.

Abstract: Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and planarizing an interlayer insulating film formed on the substrate to expose the dummy gate electrode; etching the dummy gate electrode to form a groove in an exposed portion of the substrate; implanting impurity ions into the exposed portion of the substrate to form a delta-doping layer; thermally treating the semiconductor substrate to activate the implanted impurity ions; growing a silicon film on the exposed portion of the substrate by a selective epitaxial process; depositing a gate insulating film on the surface of the groove; and depositing a gate metal film on the gate insulating film in the groove, forming the gate electrode.

Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Abstract: The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mobility.

Abstract: A semiconductor device and a method for fabricating the semiconductor device using a damascene process are disclosed. The method includes forming an Al2O3 film over a dummy gate disposed over a semiconductor substrate. Next, the dummy gate and a portion of the Al2O3 film are removed to form a groove defined by remains of the Al2O3 film and the semiconductor substrate. Then, a subsequent film is deposited within the groove, and a gate material is formed over the second film to complete the semiconductor device.

Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

Abstract: A metal gate MISFET comprises a metal gate electrode on a semiconductor substrate, a side wall insulation film, and a source-drain region which is formed on the surface of the semiconductor substrate on both sides of the side wall insulation film. Then, a cobalt silicide film is formed on the source-drain region. In this step of manufacturing the MISFET, since the cobalt silicide film is sealed with the silicon nitride film at the time of oxidizing the surface of the substrate of a gate portion, the property of the cobalt silicide film will never be deteriorated. As a consequence, the metal-gate field effect transistor having a low parasitic resistance of the source-drain region can be obtained.

Abstract: An N-channel radiation-hardened transistor has source and drain regions that are fully enclosed by an intrinsically radiation-hardened thin gate-oxide, which substantially reduces radiation-induced intra-device and inter-device leakage currents. The width of the polysilicon gate directly between the source and drain can be the minimum feature size allowed by the design rules of a given process. The width of the polysilicon surrounding the device is chosen by design rules from the minimum allowed to some wider value to allows the polysilicon overlap to be sufficient to self-align the source and drain without compromising the doping under the field region. The polysilicon should be sufficiently wide so that it completely overlaps any transitional oxide such as LOCOS or trench oxide. The gate capacitance of the N-channel transistor can be tuned to balance SEU hardness and switching performance.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof.

Abstract: A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.

Abstract: A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Abstract: A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. An FS isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes two edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of a prescribed region is smaller than a channel length at the central portion.

Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench- isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: An integrated circuit and method of fabricating integrated circuits is provided for an integrated circuit having threshold voltage adjustment. Unlike conventional methods and devices, threshold voltage adjustment is provided by an inert ion implantation process whereby inert ions are implanted into an underlying substrate. The implantation forms a semi-insulative layer comprised of an accumulation of inert ions. The inert ion region is formed between source and drain regions of a device on the integrated circuit. During operation of the device, the accumulation region confines the depth of the depletion layer. By confining the depth of the depletion layer, the threshold voltage of the device is reduced.

Abstract: A method of making metal-semiconductor compound regions, such as silicide regions, includes forming a metal layer on a surface of a semiconductor device, performing a first annealing to form metal-semiconductor regions, and depositing additional metal within and/or underneath the metal-semiconductor regions. The depositing may be accomplished by ion implantation. Following the depositing, a second annealing is performed to recrystallize the metal-semiconductor compounds and/or to increase the size of the metal-semiconductor compound regions.

Abstract: A plurality of diffusion layers extending in a first direction is formed at a surface of a semiconductor substrate in a cell region to be provided with the memory cell transistors. A plurality of gate electrodes extending in a second direction perpendicular to the first direction is formed on the semiconductor substrate in the cell regions. An interlayer insulating film is formed on the semiconductor substrate. A first resist film is formed on the interlayer insulating film. The first resist film is provided with openings in positions in alignment with regions between adjacent diffusion layers among the plurality of diffusion layers. a second resist film provided with openings previously designed in an arbitrary manner is formed on the first resist film. Then ions are implanted in the cell region using the first and second resist films as a mask.

Abstract: An inverted MOSFET process. A replacement gate (100) and removable sidewalls (80) allow the formation of spot implant regions (120) and (130) to form the pocket region (120) and the drain and source regions (130) of the MOSFET. The replacement gate (100) has a flared profile for reduced resistance.

Abstract: A gate insulating film is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed. An ONO film is formed on the side wall of the gate electrode and on the surface of the semiconductor substrate on both sides of the gate electrode, conformable to the side wall and the surface. A silicon nitride film of the ONO film traps carriers. A conductive side wall spacer faces the side wall of the gate electrode and the surface of the semiconductor substrate via the ONO film. A conductive connection member electrically connects the side wall spacer and gate electrode. Source and drain regions are formed in the surface layer of the semiconductor substrate in areas sandwiching the gate electrode. A semiconductor device is provided which can store data of two bits in one memory cell and can be driven at a low voltage.

Abstract: Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of the core transistors, which causes lower threshold voltage.

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: The semiconductor device is provided with an element isolating region disposed in a matrix to define a channel region on a semiconductor substrate, gate interconnection layers extending in a direction and disposed at predetermined intervals from each other above element isolating region, and aluminum interconnection layers extending in a direction intersecting gate interconnection layers and disposed at predetermined intervals from each other, aluminum interconnection layer being disposed above element isolating region. Thus, it becomes possible to provide a semiconductor device and a method of manufacturing thereof which enable the reduction in time required for the final manufacturing steps of the semiconductor device after the ROM specifications are determined.

Abstract: A field effect transistor (300) having a source region (304) and a drain region (306) includes a source side halo region (332) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The source side halo region is formed by implanting (408) first doping ions near the surface at the source side of the channel and implanting (410) second doping ions deeper in the channel, near the depth of a source extension (322). In this manner, optimization of leakage current of the field effect transistor is made independent of the drive current of the field effect transistor.

Abstract: A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process.

Abstract: The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantation with a large angle forms the channel of the transistor in order to prevent the punchthrough phenomenon between the source region and the drain region. In addition, the profile of the channel region is compact and non-uniform. Therefore the ion concentration is higher in the middle of the channel region than in the other regions. Thus, the parasitic capacitance and the junction leakage can be reduced. The carrier mobility is higher than that of the prior art. Moreover, the threshold voltage is more easily controlled than that of the prior art.

Abstract: A semiconductor device comprises a silicon region (1) of the first conductivity type, a porous silicon layer (2) formed inside the silicon region (1) as a buried layer and a source region (3a) and a drain region (4a) of the second conductivity type different from the first conductivity type selectively formed in an upper surface of the silicon region (1). Bottom surfaces of the source region (3a) and the drain region (4a) are located adjacently above an upper surface of the porous silicon layer (2). As a result, depletion layers (8) in pn junctions between the silicon region (1) and the bottom surfaces of the source region (3a) and the drain region (4a) reach the inside of the porous silicon layer (2). With this structure, a semiconductor device which achieves a faster operation and lower power consumption while ensuring stability in operation of a MOSFET and a method of manufacturing the same are provided.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: An improved method of forming an MOS transistor, which includes forming a polysilicon layer on a silicon dioxide layer, which is formed on a substrate. After etching the polysilicon and silicon dioxide layers to define a gate electrode and a gate oxide, dopants are implanted into the substrate. Following that implantation step, the exposed portion of the gate oxide is cleaned and sealed.