Abstract: A method for processing semiconductor wafers is disclosed. A semiconductor wafer is provided to a semiconductor processing stage where a block copolymer surfactant (BCS) is applied to the wafer surface. In one embodiment, the BCS includes a hydrophobic portion and a hydrophilic portion. Alternatively, the BCS may be a silicone-containing BCS. In one embodiment, the BCS is within an aqueous solution where the concentration of the BCS within the aqueous solution is less than one percent by weight. Also disclosed is an aqueous solution including abrasive particles and a BCS having a hydrophobic portion and a hydrophilic portion. The abrasive particles may include silica, alumina, or ceria.

Abstract: A method of adjusting the in-plane lattice constant of a substrate and an in-plane lattice constant adjusted substrate are provided. A crystalline substrate (1) made of SrTiO3 is formed at a first preestablished temperature thereon with a first epitaxial thin film (2) made of a first material, e. g., BaTiO3, and then on the first epitaxial thin film (2) with a second epitaxial thin film (6) made of a second material, e. g., BaxSr1-xTiO3 (where 0<x<1), that contains a substance of the first material and another substance which together therewith is capable of forming a solid solution in a preestablished component ratio. Thereafter, the substrate is heat-treated at a second preselected temperature. Heat treated at the second preestablished temperature, the substrate has dislocations (4) introduced therein and the second epitaxial thin film (6) has its lattice constant relaxed to a value close to the lattice constant of bulk crystal of the second material.

Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.

Abstract: Methods of fabricating uniform nanotubes are described in which nanotubes were synthesized as sheaths over nanowire templates, such as using a chemical vapor deposition process. For example, single-crystalline zinc oxide (ZnO) nanowires are utilized as templates over which gallium nitride (GaN) is epitaxially grown. The ZnO templates are then removed, such as by thermal reduction and evaporation. The completed single-crystalline GaN nanotubes preferably have inner diameters ranging from 30 nm to 200 nm, and wall thicknesses between 5 and 50 nm. Transmission electron microscopy studies show that the resultant nanotubes are single-crystalline with a wurtzite structure, and are oriented along the <001> direction. The present invention exemplifies single-crystalline nanotubes of materials with a non-layered crystal structure. Similar “epitaxial-casting” approaches could be used to produce arrays and single-crystalline nanotubes of other solid materials and semiconductors.

Abstract: A method for forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide is disclosed. In one aspect, a method for forming a nanolaminate of silicon oxide on a substrate is disclosed. In another aspect, a method for forming a patterned hard mask on a substrate is disclosed. The patterned hard mask includes a nanolaminate of silicon and silicon oxide. The methods are characterized by the oxidation of an amorphous silicon layer using atomic oxygen.

Abstract: A method of manufacturing a ferroelectric memory of the present invention includes applying pulsed laser light 70 to a ferroelectric capacitor 105 from above the ferroelectric capacitor in a state in which at least the ferroelectric capacitor 105 is formed over a substrate 10.

Abstract: A method for fabricating a closed-form Josephson junction includes etching the inner shape of the closed-form junction on the chip, depositing a negative photoresist material over the etched chip, and flood exposing the backside of the chip with ultraviolet radiation. The photoresist is developed and then baked onto the chip. The baked photoresist serves as a mask for subsequent etching of the exterior of the closed-form Josephson junction. A shaped Josephson junction is fabricated with junction widths between about 0.1 &mgr;m and about 1 &mgr;m and an inner diameter ranging between about 1 &mgr;m and about 1000 &mgr;m.

Abstract: A Josephson junction has a Si substrate, a two layer film comprising an amorphous MgO layer and a high orientation MgO layer on the Si substrate, and a NbN film or the NbCN film laminated on the two layer film.

Abstract: The present invention provides a process for preparing a transplantable liver tissue, cell colonies suitable for the process, and a process for preparing them. At least about 70% of the cells in the small hepatocyte-rich colonies of the present invention are small hepatocytes. In particular, each colony comprises about 10 to 30 cells and the number of the small hepatocytes is at least about 70% based on the total number of the cells in the colony. A process for preparing such small hepatocyte-rich colonies is also disclosed. The present invention also discloses a process for inducing the maturation of the small hepatocyte-rich colonies into a liver tissue and a method of estimating the effect of a drug, particularly the effect thereof connected with normal liver function in vitro, using the cell colonies enriched with the small hepatocytes which have been induced to be matured.

Abstract: A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.

Abstract: Thin films of conducting and superconducting materials are formed by a process which combines physical vapor deposition with chemical vapor deposition. Embodiments include forming boride films, such as magnesium diboride, in high purity with superconducting properties on substrates typically used in the semiconductor industry by physically generating magnesium vapor in a deposition chamber and introducing a boron containing precursor into the chamber which combines with the magnesium vapor to form a thin boride film on the substrate.

Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A &lgr;/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.

Abstract: A superconductor integrated circuit (10) includes a silicon substrate (12) a niobium ground layer (14), an anodized niobium first ground insulator layer (16), a second ground insulator layer (22), a molybdenum nitrogen (MoNx) resistor (18) provided between the first and second ground insulator layers (16, 22), a Josephson junction (23) provided above the first and second ground insulator layers (16, 22), first and second oxide insulators (27, 30), and a niobium interconnect (28) for providing electrical communication with the Josephson junction. The MoNx first resistor (18) provides a sheet resistance of between 3-5 ohms/sq at 4° K with a thickness of approximately 95 nm and enables the superconductor integrated circuit (10) to have a critical current density between 6-8 kA/cm2.

Abstract: A method for fabricating a laser for generating single-longitudinal mode laser light at a lasing wavelength. A semiconductor active region for amplifying, by stimulated emission, light in the laser cavity at the lasing wavelength is formed. A grating is formed adjacent to the active region, the grating having a grating period corresponding to a Bragg wavelength substantially equal to the lasing wavelength. An intermediate section of the grating is removed to result in first and second pluralities of gratings separated by a gratingless intermediate section. First and second grating sections are formed comprising the first and second pluralities of gratings, where the first and second grating sections each have a first effective index of refraction.

Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.

Abstract: A superconducting qubit is presented. The qubit is a shaped long Josephson junction with a magnetic fluxon such that, in the presence of an externally applied magnetic field, a fluxon potential energy function indicating a plurality of pinning sites in the qubit is produced. In one embodiment, a heart-shaped Josephson junction is formed where a trapped fluxon has a double-welled potential energy function, indicating two pinning sites, when the junction is placed in an externally applied magnetic field. The qubit is manipulated by preparing an initial state, creating a superposition of the two states by decreasing the magnetic field, evolving of the quantum state with time, freezing in a final state by increasing the magnetic field, and reading out the final state. In other embodiments, qubit exhibiting potential energy functions having any number of pinning sites can be realized.

Abstract: The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method. A memory for identifying a 128-bit identification number, which makes use of a transistor, is configured by each contact hole selectively defined by an electron-beam writing method. A plane long-side size of a semiconductor chip is set to 0.5 mm or less. The contact holes are defined simultaneously with contact holes for peripheral circuits. In addition, the plane long-side size of the semiconductor chip is set smaller than the thickness of a wafer prior to the start of its manufacture and set larger than the thickness of the post-thinning wafer. Otherwise, the same data as a barcode is further stored in the memory. Additionally, data obtained by enciphering the identification number is used to test or inspect the semiconductor chip.

Abstract: In a process for patterning both sides of a double-sided HTS thin film wafer with the patterns in close registration, the first side is patterned with at least one reference mark and the second side is patterned with at least one aperture which permits alignment of the reference mark from the already applied pattern on the first side preferably to a similar reference mark on the yet to be applied patterns on the second side, such that the patterns can be aligned in close registration, using microcopic viewing techniques if necessary.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: An electrically stabilized thin-film high-temperature superconductor includes a superconductive layer (32) applied over a flat metallic substrate (31) and connected to the metallic substrate (31) so that electrical contact between the superconductive layer (32) and the metallic substrate (31) is distributed over the area of the metallic substrate (31).

Abstract: A method for fabricating a closed-form Josephson junction includes etching the inner shape of the closed-form junction on the chip, depositing a negative photoresist material over the etched chip, and flood exposing the backside of the chip with ultraviolet radiation. The photoresist is developed and then baked onto the chip. The baked photoresist serves as a mask for subsequent etching of the exterior of the closed-form Josephson junction. A shaped Josephson junction is fabricated with junction widths between about 0.1 &mgr;m and about 1 &mgr;m and an inner diameter ranging between about 1 &mgr;m and about 1000 &mgr;m.

Abstract: A solid state dc-SQUID includes a superconducting loop containing a plurality of Josephson junctions, wherein an intrinsic phase shift is accumulated through the loop. In an embodiment of the invention, the current-phase response of the dc-SQUID sits in a linear regime where directional sensitivity to flux through the loop occurs. Changes in the flux passing through the superconducting loop stimulates current which can be quantified, thus providing a means of measuring the magnetic field. Given the linear and directional response regime of the embodied device, an inherent current to phase sensitivity is achieved that would otherwise be unobtainable in common dc-SQUID devices without extrinsic intervention.

Abstract: A method of forming a step edge in a surface 12 of a crystalline substrate 10, comprising the steps of forming a layer of resist 11 over the surface 12 and removing areas of the resist 11 to expose selected areas of the surface 12, thereby forming side walls 13 in the layer of the resist 11, the side walls 13 bounding the exposed areas of the surface 12. The method further comprises exposing the resist 11 and substrate 10 to an ion beam 14, thereby etching the resist 11 and the exposed areas of the surface 12, and controlling the orientation and angle of incidence of the ion beam 14 which respect to the substrate 10 and the resist side walls 13 to form a step edge with desired angle and height characteristics. An angular position of the substrate 10 about an axis 15 formed by a normal to the surface 12 is controlled in order to control the step edge formation.

Abstract: Methods and systems are provided for depositing a magnetic film using one or more long throw magnetrons, and in some embodiments, an ion assist source and/or ion beam source. The long throw magnetrons are used to deposit particles at low energy and low pressure, which can be useful when, for example, depositing interfacial layers or the like. An ion assist source can be added to increase the energy of the particles provided by the long throw magnetrons, and/or modify or clean the layers on the surface of the substrate. An ion beam source can also be added to deposit layers at a higher energies and lower pressures to, for example, provide layers with increased crystallinity. By using a long throw magnetron, an ion assist source and/or an ion beam source, magnetic films can be advantageously provided.

Abstract: A semiconductor device including a damascene superconducting interconnect, formed of a Ba—Cu—Ca—O superconducting material. A method of forming a superconducting damascene interconnect structure, and the structure made thereby, the method including forming a cavity in an interlevel dielectric; forming a barrier layer in the cavity; forming a seed layer in the cavity over the barrier layer; forming a Cu—Ba alloy layer; filling the cavity by depositing a Cu—Ca—O film; and annealing in oxygen flow to form a Ba—Cu—Ca—O superconductor on the barrier layer. In an alternate embodiment, no barrier layer is formed.

Abstract: A high temperature superconducting Josephson junction device with ramp-edge geometry in which silver is combined in a composite with YBa2Cu3O7, yttrium-barium-copper-oxide, to form the electrodes, or PrBa2Cu3O7, praseodymium-barium-copper-oxide, to form the weak link.

Abstract: A portion, positioned at an opening portion of a resist, of an anti-reflection film is etched using an etching gas containing a substituted hydrocarbon with a halogen. At the time of etching of the anti-reflection film, a carbon component of the substituted hydrocarbon with a halogen is formed as a carbonaceous deposit on side walls , less irradiated with ions, of the opening portion of the resist, and on side walls of an opening portion, formed by etching, of the anti-reflection film. The deposit acts as a side wall blocking film, to suppress lateral extension of the opening portion of the resist and the opening portion of the anti-reflection film by etching, thus allowing anisotropic etching of the anti-reflection film. With this etching method, it is possible to etch the anti-reflection film with a resist taken as a mask while suppressing a variation in pattern dimension.

Abstract: An apparatus for communications by a home station among remote stations in at least one communication medium. The apparatus comprises (a) local signal receiving circuitry for receiving an originating signal containing local intelligence; and (b) local signal processing circuitry for conveying the local intelligence via a communication medium to a target remote station; (c) remote signal receiving circuitry for receiving a transmitted signal containing remote intelligence; and (d) remote signal processing circuitry coupled with the remote signal receiving circuitry for processing the transmitted signal for conveying the remote intelligence to a user. The local signal receiving circuitry, the local signal processing circuitry, the remote signal receiving circuitry and the remote signal processing circuitry are implemented in a unitary structure borne upon a single silicon substrate.

Abstract: A method of forming a superconducting damascene interconnect structure, and the structure made thereby, the method includes forming a cavity in an interlevel dielectric; forming a barrier layer in the cavity; forming a seed layer in the cavity over the barrier layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the barrier layer. In one embodiment, the superconductor has a formula YBa2Cu3O7-x, wherein x≦0.5. In another embodiment, the method includes forming a cavity in an interlevel dielectric; forming a Y—Ba—Cu alloy layer in the cavity; forming a seed layer in the cavity over the Y—Ba—Cu alloy layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy fill; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the dielectric.

Abstract: The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm. The present invention also provides a method for forming Au and other metal nanowires that may be used for electrical conductors and both positive and negative etch masks to form a plurality of ridges at a pitch of 0.94 to 5.35 nm containing at least two adjacent grooves with widths of 0.63 to 5.04 nm.

Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.

Abstract: A leadframe including offsets extending from a major plane thereof The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: A ceramics fabricating method which includes a step of forming a ceramic film by feeding an electromagnetic wave and an active species of a substance which is at least part of raw materials for the ceramics to a predetermined region. A film including a substance which is part of the raw materials for the ceramics may be formed in the predetermined region. The fabrication method further includes a step of feeding the active species and the electromagnetic wave to a first ceramic film to form a second ceramic film which has a crystal structure differing from that of the first ceramic film.

Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristic conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: A method for manufacturing a semiconductor device capable of suppressing the electric charge as charged up in a semiconductor layer of an SOI substrate at the time of the ion implantation, thus preventing a BOX layer and a gate oxide from being damaged. By means of LOCOS method, a field oxide film 20 is formed on a semiconductor layer 18 which is formed on a BOX layer 16 making up of the SOI wafer 12 of a semiconductor device 100. A conductive layer 102 is formed on the field oxide film 20 and a gate oxide film 26 as well. The conductive layer 102 made of amorphous carbon is formed by means of the sputtering method and has a thickness of 5 nm to 10 nm. B+24 is implanted in the interface between the semiconductor layer 18 and the gate oxide film 22 by means of an intermediate dose ion implanter. The electric charge 38 generated in the semiconductor layer 18 at the time of the ion implantation results in the FN current, which is removed through the gate oxide film 22 and the conductive layer 102 as well.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t≦r≦35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 &mgr;m to 30 &mgr;m and larger than that of the second curved surface.

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract: A process which relies on a joining technique between two individual strongly linked superconductors is disclosed. Specifically, this invention relates to fabrication of single domains of YBa2Cu3Ox or YBa2Cu3Ox with the addition of Y2BaCuO5 and/or other secondary phases such as Pt/PtO2, CeO2, SnO2, Ag, Y2O3 and other rare earth oxides, by using a top-seeded, melt processing technique. Beginning with a single crystal seed such as Nd1+xBa2−xCu3Ox or SmBa2Cu3Ox crystals, a melt-textured YBCO domain with crystallographic orientation nearly similar to that of the seed crystal can be fabricated. The samples are next machined to desired geometrical shapes. A bonding material is then applied to the ac plane. Low solidification or recrystalization point, similar crystal structure to that of YBa2Cu3Ox, and capability of growing epitaxially on YBCO domains are critical parameters of the bonding material.

Abstract: A circuit device is disclosed comprising at least two circuit layers interconnected with a plurality of substantially equi-length nanowires disposed therebetween. The nanowires may comprise composites, e.g., having a heterojunction present along the length thereof, to provide for a variety of device applications. Also disclosed is a method for making the circuit device comprising growing a plurality of nanowires in-situ on at least one circuit substrate and then interconnecting the nanowires to a mating substrate.

Abstract: Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: A method of forming a gate oxide layer according to the invention is disclosed. In the method, a furnace or rapid thermal oxidation (RTO) chamber where a semiconductor substrate having a native oxide layer formed thereon is located is supplied with a high-temperature hydrogen gas to deoxidize the native oxide layer. Then, a gate oxide layer is formed over the semiconductor substrate. The semiconductor substrate having the gate oxide layer formed thereon is transferred through a vacuum transmission system into a reaction chamber where a polysilicon layer is formed on the gate oxide layer. Thus, the semiconductor substrate can avoid exposure to an oxygen-containing atmosphere to re-form a native oxide layer thereon.

Abstract: High-capacity capacitors and gate insulators exhibiting moderately high dielectric constants with surprisingly low leakage using amorphous or low temperature films of perovskite type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, a niobate, aluminate or tantalate system material such as lead magnesium niobate, lithium niobate lithium tantalate, potassium niobate and potassium tantalum niobate, a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate, and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate deposited directly on a silicon surface at temperatures about 450° C. or less.

Abstract: The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: A method for forming high frequency connections between a fragile chip and a substrate is described, wherein metal is selectively deposited on a surface of a chip and a surface of a substrate, and corresponding patterns of electrically conductive bumps are selectively evaporated on the surface of the chip and the surface of the substrate over the metal layers, to form a pattern of electrically conductive bumps having spongy and dendritic properties, placing the chip in aligned contact with the substrate where each electrically conductive chip bump mates with each corresponding electrically conductive substrate bump, and selectively applying heat and pressure to the chip and substrate causing each chip bump to fuse together with each corresponding substrate bump to form an electromechanical bond.

Abstract: A method of forming a tunnel barrier layer that includes at least a single oxide layered region in an intermediate layer sandwiched between first and second ferromagnetic layers. An electrically conductive layer is formed on the first ferromagnetic layer. The electrically conductive layer is subjected to an exactly pure oxygen gas prepared by introducing oxygen into a vacuum, so as to oxidize the electrically conductive layer, thereby to form an oxide layer forming a tunnel barrier. The second ferromagnetic layer is formed on the oxide layer.