Abstract: According to one aspect, provided is a junction between tape-type superconductors, which are formed of metal-coated oxide superconductors. The superconductors of the superconducting wires, which are oppositely joined to each other, are overlapped with each other. According to another aspect, provided is a method of joining tape-type superconducting wires formed of metal-coated oxide superconductors, which comprises a step of preparing tape-type superconducting wires having portions to be joined, a step of separating metal coatings from first sides of the superconductors in the portions to be joined for exposing the superconductors, a step of overlapping the exposed superconductors with each other, and a step of joining the overlapped superconductors to each other. In the junction obtained according to these aspects, it is possible to stably carry a uniform superconducting current.

Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Abstract: A multilayer ceramic substrate electronic component is provided having high temperature superconductor material circuitry. The high temperature superconductor material is preferably yttrium-barium-copper-oxide and is encased within a noble metal such as silver or gold when forming the surface circuitry or filling of the vias. The noble metal layers preferably have through-openings to enable direct connection of circuitry to the encased superconductor layer. A method is also provided for fabricating such multilayer ceramic substrate electronic components.

Abstract: A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18.

Abstract: A magnetic sensor comprises a SQUID made of a superconducting thin film. The superconducting thin film has a washer pattern and a terminal portion. The washer pattern has a non-square one hole pattern and a pair of slit patterns. The hole pattern has rectangle shape and includes the center of the washer pattern. The slit patterns having a straight shape growing parallel to the long side of the hole pattern, from the outside edge of the washer pattern toward the inside of the washer pattern. This outside edge of the washer pattern is the nearest to the hole pattern. There is an artificial grain boundary in the domain that spacing between the hole pattern and the slit pattern is narrowest. There is no artificial grain boundary in the other domain at all.

Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: In a Josephson junction device comprises two superconducting electrodes formed of an oxide superconductor and connected through a Josephson junction, a temperature dependent noise of the Josephson junction becomes the minimum at a liquid nitrogen temperature.

Abstract: A plurality of single crystal grains made of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 which are heat treated at a temperature that is equal to or higher than the crystallization temperature of an oxide high-temperature superconductor made of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 and are surrounded by a grain boundary are formed on a substrate made of a MgO single crystal. A convex portion having a sectional area of 400 .mu.m.sup.2 or less and a height which is equal to or less than ten times as much as a space between block layers of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 is formed on the upper face portion of the single crystal grain. A first electrode made of Au is formed on the upper face of the convex portion of the single crystal grain, and a second electrode is formed in a region other than the convex portion in the single crystal grain. The first electrode is insulated from the second electrode by an insulating film made of CaF.sub.2.

Abstract: A method of manufacturing super conduction field effect transistor having a bi-crystal boundary junction is disclosed. According to the present invention, it is constituted such that on a SrTiO.sub.3 bi-crystal substrate, a bi-crystal super conductive thin films for source and drain electrode having a compound of YBa.sub.2 Cu.sub.3 O.sub.7-x, a non-super conductive oxide layer having a compound of PrBa.sub.2 Cu.sub.3 O.sub.7-x interposed between the bi-crystal super conductive thin films for source and drain electrode and the SrTiO.sub.3 bi-crystal substrate, a boundary channel interposed therebetween, a amorphous insulating layer for gate electrode having a compound of SrTiO.sub.

Abstract: Disclosed is a method for making a superconducting field-effect device with a grain boundary channel, the method comprising the steps of depositing a first superconducting thin film on a substrate; patterning the first superconducting thin film to form a patterned superconducting thin film having an opening; depositing a template layer thereon; selectively etching back the template layer to form a patterned template layer; growing a second superconducting thin film to form a grain boundary therebetween; depositing an insulating layer on the second superconducting thin film to protect the second superconducting thin film from degrading in property in the air; selectively etching back the insulating layer to form a patterned insulating layer; forming a gate insulating layer on the patterned insulating layer; and coating metal electrodes thereon, source/drain being formed respectively on the etched portions, and a gate electrode being formed on the deposited portion of the gate insulating layer directly above th

Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.

Abstract: A multilayer thin film of the invention has an oxide thin film formed on a semiconductor single crystal substrate, and the oxide thin film includes at least one epitaxial thin film composed mainly of zirconium oxide or zirconium oxide stabilized with a rare earth metal element (inclusive of scandium and yttrium). Included is an oriented thin film formed on the oxide thin film from a dielectric material of perovskite or tungsten bronze type with its c-plane unidirectionally oriented parallel to the substrate surface. Consequently, there are provided a perovskite oxide thin film of (001) orientation, a substrate for an electronic device comprising the thin film, and a method for preparing the thin film.

Abstract: In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

Abstract: A superconductive electrical device is operable simultaneously at relatively higher temperatures, i.e., 60-90K, and at relatively lower temperatures, i.e., less than 12K. The device comprises a non-superconductive substrate with two regions, a first relatively high temperature region and a second relatively low temperature region. A high temperature superconductor is on the first region and a portion of the second region. A dielectric layer is on the high temperature superconductor. A low temperature superconductor is on the second region of the substrate and on a portion of the dielectric layer. Integrated circuit chips can be secured to both superconductors, thereby yielding a superconductive multi-chip module operable at two different temperatures, such as in a cryo-cooler with two temperature stages.

Abstract: The invention relates to a high temperature superconducting electric field effect device which creates a dual grain boundary on a superconducting thin film and employs it as a channel. The device comprises a substrate, a bottom layer formed on a predetermined region of the bottom layer, a dual grain boundary channel region formed on the bottom layer, a high temperature source and a drain formed at both end portions of the channel region on the substrate, a high temperature superconducting thin film channel layer formed a predetermined region on the source, the drain and the substrate, dual grain boundaries formed on the high temperature superconducting thin film channel layer, and a gate insulating layer formed on the dual grain boundary channel region.

Abstract: Disclosed is a method for making a high-temperature super-conducting field-effect transistor with a thick super-conducting channel, the method comprising the steps of depositing a template layer on an oxide crystal substrate by using a pulse laser depositing apparatus; forming a YBa.sub.2 Cu.sub.3 O.sub.7-x layer on the template layer; patterning the YBa.sub.2 Cu.sub.3 O.sub.7-x layer to form a patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer having an opening and expose a surface portion of the template layer; depositing a YBa.sub.2 Cu.sub.3 O.sub.7-x channel layer on the surface portion of the template layer and over the patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer, the channel layer having a thickness of from 60 to 100 nm; sequentially forming an SrTiO.sub.3 protective layer and an SrTiO.sub.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.