Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.

Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.

Abstract: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 toward a main surface of the semiconductor substrate 1 in the base extraction electrode 5B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film 4 interposed between the main surface of the semiconductor substrate 1 and a lower surface of the base extraction electrode 5B.

Abstract: The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface of a channel region. This structure allows the formation of a relatively a thick channel region and decreases the sensitivity of characteristics of the device dependent upon the thickness of the channel region.

Abstract: A method for producing a bipolar transistor is described, which comprises providing a layer sequence, which comprises a substrate, a first oxide layer and a SOI layer, generating a collector region in the substrate, generating a second oxide layer on the layer sequence, generating a base region in the first oxide layer, such that the base region is in contact with the SOI layer, generating an emitter region on the base region such that the emitter region is isolated from the SOI layer, and generating a collector contact, a base contact and an emitter contact. The present invention is based on the knowledge that the production of a bipolar transistor can be made significantly less expensive when the above layer sequence is used for its production, and thereby, the base region is generated in the BOX layer while the collector region is formed in the substrate. Thereby, otherwise required production process steps and particularly layer deposition steps, such as for a polysilicon or oxide layer, are saved.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.

Abstract: A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insulating layer. A transistor area opening is etched through the conductive layer, and an SiGe base layer is deposited inside the transistor area opening. An insulator is formed on an upper surface so as to fill the transistor area opening, wherein prior to filling the opening, a nitride layer is formed as an inner layer of the transistor area opening.

Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si cap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.

Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, higher order silanes are employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film comprised of a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.

Abstract: Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.

Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Abstract: A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).

Abstract: The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer of epitaxial material. After this, a base material that includes silicon and germanium is blanket deposited, followed by the blanket deposition of a layer of protective material. The layer of protective material protects the base material from the chemical mechanical polishing step.

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: A heterojunction bipolar transistor includes an emitter layer, a base layer and a collector layer laminated on a top surface of a semiconductor substrate, and a heat sink layer made of a metal and provided on a rear surface of the substrate. A via hole is cut through the emitter layer, the base layer, the collector layer and the substrate. A surface electrode of the emitter layer and the heat sink layer are connected to each other by a metal wiring line running through within the via hole, which is capable of improving the heat radiation and reducing the emitter inductance.

Abstract: A first aspect of the invention is to realize a power amplifier having high power adding efficiency and high power gain at low cost. For that purpose, in a semiconductor device using an emitter top heterojunction bipolar transistor formed above a semiconductor substrate and having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. In this way, as a result of enabling to reduce base/collector junction capacitance per unit emitter area without using a collector top structure having complicated fabricating steps, a semiconductor device having high power adding efficiency and high-power gain and suitable for a power amplifier can be realized.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Abstract: A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Abstract: A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.

Abstract: One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the first wafer is transferred from the undoped epi chamber into a separate doped epi chamber. A first doped base layer is then grown over the first undoped based layer in the doped epi chamber. While the first wafer is being processed in the doped epi chamber, a second wafer can be processed in the undoped epi chamber. Another embodiment is a structure produced by the disclosed method and yet another embodiment comprises a transfer chamber, a transfer arm, a bake chamber, and a separate undoped epi chamber and a doped epi chamber for practicing the disclosed method.

Abstract: Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: In the fabrication of a silicon bipolar transistor, a method for forming base regions and for opening an emitter window is provided. A silicon substrate is provided with suitable device isolation. A first base region is formed in or on top of the substrate. A thin layer of oxide is formed on the first base region. A layer of silicon is formed on top of the thin oxide layer, the silicon layer is to be a second base region. The silicon layer is ion implanted. A layer of a dielectric is formed on top of the silicon layer, the dielectric is to isolate base and emitter regions of the transistor. The obtained structure is patterned in order to define the emitter window. The structure inside the defined emitter window area is etched and through the dielectric and silicon layers, wherein the thin oxide layer is used as etch stop, thus forming the emitter window. The structure is subsequently heat treated and thus break up the oxide such that the first and second base regions will contact each other.

Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Abstract: A process for forming a silicon-germanium base of a heterojunction bipolar transistor. First, a silicon substrate having a mesa surrounded by a trench is formed. Next, a silicon-germanium layer is deposited on the substrate and the portion of the silicon-germanium layer adjacent the mesa is removed to form the silicon-germanium base. In a second embodiment, the process comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, forming a dielectric layer in the trench adjacent the mesa, and growing a silicon-germanium layer on the mesa top surface using selective epitaxial growth to form the silicon-germanium base.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: A method for producing a heterobipolar transistor, arranged on a substrate of semiconductor material on which is grown a semiconductor sequence for a collector, a base and an emitter, which method includes: etching the layer sequence to form a transistor with a mesa structure, carrying out a first planarizing step to the upper limit of the base during which the surface of the base is protected by a protecting portion of the emitter layer adjacent to the base; removing this protective layer; depositing a metal contact layer for the base; carrying out a second planarizing step for the base emitter mesa; and finally depositing a connecting metallization layer for the collector, base and emitter.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.