Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.

Abstract: The present invention generally relates to a thermal processing apparatus and method that permits a user to index one or more preselected light sources capable of emitting one or more wavelengths to a collimator. Multiple light sources may permit a single apparatus to have the capability of emitting multiple, preselected wavelengths. The multiple light sources permit the user to utilize multiple wavelengths simultaneously to approximate “white light”. One or more of a frequency, intensity, and time of exposure may be selected for the wavelength to be emitted. Thus, the capabilities of the apparatus and method are flexible to meet the needs of the user.

Abstract: According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity type arranged between the body and a bottom contact layer. An integrated diode is formed partially by a first zone of the first conductivity type within the body and being in contact with the top contact layer and a second zone of the second conductivity type being in contact with the bottom contact layer. A reduced charge carrier concentration region is formed in the drift zone having a continuously increasing charge carrier lifetime in the vertical direction so that the charge carrier lifetime is lowest near the body and highest near the bottom contact layer.

Abstract: Methods for compensating for a thermal profile in a substrate heating process are provided herein. In some embodiments, a method of processing a substrate includes determining an initial thermal profile of a substrate that would result from subjecting the substrate to a process; determining a compensatory thermal profile based upon the initial thermal profile and a desired thermal profile; imposing the compensatory thermal profile on the substrate prior to performing the process on the substrate; and performing the process to create the desired thermal profile on the substrate. The initial substrate thermal profile can also be compensated for by adjusting a local mass heated per unit area, a local heat capacity per unit area, or an absorptivity or reflectivity of a component proximate the substrate prior to performing the process. Heat provided by an edge ring to the substrate may be controlled prior to or during the substrate heating process.

Abstract: When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of the TFTs will be adversely influenced. A concentric-circle pattern is formed by the interference between a reflected beam 1 reflected at a surface of a semiconductor film and a reflected beam 2 reflected at the back surface of a substrate. If the reflected beam 1 and the reflected beam 2 do not overlap each other, such interference does not occur. For this reason, a laser beam is obliquely irradiated onto the semiconductor film to solve the interference. The properties of a crystalline silicon film formed by this method are uniform, and TFTs which are fabricated by using such crystalline silicon film have good electrical characteristics.

Abstract: A mounting structure for an IC tag where an IC chip for mounting (10) is mounted so as to be electrically connected to antenna patterns (44a), (44b). The assembly process that mounts the IC chip for mounting (10) on the antenna patterns (44a), (44b) is simplified, which makes it possible to reduce the manufacturing cost of IC tags. The IC chip for mounting 10 is formed by winding conductive wires (12a), (12b) so as to encircle an outer surface of an IC chip (20) between two opposite edges of the IC chip (20) in a state where the conductive wires (12a), (12b) mechanically contact electrodes formed on the IC chip (20) and are electrically connected to the electrodes, so that the IC chip for mounting (10) is joined to the antenna patterns (44a), (44b) via the conductive wires (12a), (12b).

Abstract: A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49phase titanium silicide.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an emitter region of the second conductivity type into the base region; forming an emitter in the emitter region, and forming a collector in the collector region; and forming a base in the semiconductor substrate through implanting high concentration impurity ions of the first conductive type into the semiconductor substrate.

Abstract: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.

Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.

Abstract: A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

Abstract: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer deposition. The diode is preferably formed of deposited low-defect semiconductor material, crystallized in contact with a silicide. A monolithic three dimensional memory array of such cells can be formed in stacked memory levels above the wafer substrate.

Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.

Abstract: A method for forming a silicon-containing insulation film on a substrate by plasma polymerization includes: introducing a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon cyclic compound containing at least one vinyl group (Si-vinyl compound), and (ii) an additive gas, into a reaction chamber where a substrate is placed; and applying radio-frequency power to the gas to cause plasma polymerization, thereby depositing an insulation film on the substrate.

Abstract: Methods for compensating for a thermal profile in a substrate heating process are provided herein. In one embodiment, a method of processing a substrate includes determining an initial thermal profile of a substrate resulting from a process; imposing a compensatory thermal profile on the substrate based on the initial thermal profile; and performing the process to create a desired thermal profile on the substrate. In other embodiments of the invention, the initial substrate thermal profile is compensated for by adjusting a local mass heated per unit area, a local heat capacity per unit area, or an absorptivity or reflectivity of a component proximate the substrate prior to performing the process. In another embodiment, the heat provided by an edge ring to the substrate may be controlled either prior to or during the substrate heating process.

Abstract: A method for manufacturing thin film semiconductor device is provided. The semiconductor thin film includes a semiconductor thin film and a gate electrode and has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part that is the active region overlapping with the gate electrode, a crystalline state is changed cyclically in a channel length direction, and areas each having a substantially same crystalline state traverse the channel part.

Abstract: A method includes forming a fluid including an inorganic semiconductor material, depositing a layer of said fluid on a substrate to form a film, and curing said film to form a porous semiconductor film.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.

Abstract: For manufacture of a semiconductor device using a low heat resistant substrate such as a glass substrate, a method of heat treatment for activating an impurity element that is used to dope a semiconductor film and for performing gettering on the semiconductor film in a short period of time without deforming the substrate, is provided. Also provided is a heat treatment apparatus for carrying out the above heat treatment. The heat treatment method of the present invention involves irradiating an object with light emitted from a lamp light source, and is characterized in that the lamp light source emits light for 0.1 to 20 seconds at a time and that light from the lamp light source irradiates the object several times. The method is also characterized in that the irradiated region is subjected to pulsating light from the lamp light source such that the irradiated region holds the temperature to its highest for 0.5 to 5 seconds.

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Abstract: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Abstract: Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench (14) formed on a silicon substrate (16) having opposed silicon oxide side walls (12); selectively growing a highly doped mono-crystalline layer (18) on the silicon substrate in the trench; and non-selectively growing a silicon layer (20) over the trench in order to form an amorphous polysilicon layer over the silicon oxide sidewalls.

Abstract: A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.

Abstract: Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and an emitter region may be defined by a CMOS mask.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is permanently magnetic such that the semiconductor chip is magnetically fixed on the chip carrier.

Abstract: A method comprising providing a substrate and forming a device on the substrate, wherein forming the device includes printing at least one region of inorganic semiconductor on the substrate.

Abstract: It is an object of the present invention to provide a method for removing the metal element from the semiconductor film which is different from the conventional gettering step for removing the metal element from the semiconductor film. In the present invention, when Ni element (Ni) is used as the metal element and a silicon-based film (referred to as a silicon film) is used as the semiconductor film, nickel silicide segregates in the ridge formed in the silicon film by irradiating the pulsed laser light. Next, etching solution of hydrofluoric acid based etchant is used to remove the nickel silicide segregated in the ridge. When the surface of the semiconductor film is rough after removing the metal element by means of etching, the laser light may be irradiated to the semiconductor film under the insert atmosphere to flatten the surface thereof.

Abstract: A method for making condenser microphones includes: forming a fixed electrode layer structure of a plurality of fixed electrode units; forming a sacrificial layer of a plurality of sacrificial units on one side of the fixed electrode layer structure; forming a diaphragm layer structure of a plurality of diaphragm units on the sacrificial layer; forming a patterned mask layer on an opposite side of the fixed electrode layer structure opposite to the sacrificial layer; forming a plurality of etching channels, each of which extends through the patterned mask layer and the fixed electrode layer structure; removing a portion of the sacrificial layer of each of the sacrificial units so as to form a spacer between a respective one of the fixed electrode units and a respective one of the diaphragm units; and removing the patterned mask layer.

Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.

Abstract: A system and method is disclosed for providing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.

Abstract: Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the substrate (2).

Abstract: A polysilicon thin film fabrication method is provided, in which a heat-absorbing layer is used to provide sufficient heat for grain growth of an amorphous silicon thin film, and an insulating layer is used to isolate the heat-absorbing layer and the amorphous silicon thin film. A regular heat-conducting layer is used as a cooling source to control the crystallization position and grain size of the amorphous silicon thin film. Therefore, the amorphous silicon thin film can crystallize into a uniform polysilicon thin film, and the electrical characteristics of the polysilicon thin film can be stably controlled.

Abstract: When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of the TFTs will be adversely influenced. A concentric-circle pattern is formed by the interference between a reflected beam 1 reflected at a surface of a semiconductor film and a reflected beam 2 reflected at the back surface of a substrate. If the reflected beam 1 and the reflected beam 2 do not overlap each other, such interference does not occur. For this reason, a laser beam is obliquely irradiated onto the semiconductor film to solve the interference. The properties of a crystalline silicon film formed by this method are uniform, and TFTs which are fabricated by using such crystalline silicon film have good electrical characteristics.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.

Abstract: The present invention is directed to an apparatus and process for locally heating and/or cooling of semiconductor wafers in thermal processing chambers. In particular, the apparatus of the present invention includes a device for heating or cooling localized regions of a wafer to control the temperature of such regions during one or more stages of a heat cycle. In one embodiment, gas nozzles eject gas towards the bottom of the wafer to provide localized temperature control. In another embodiment, a transparent gas pipe containing a variety of gas outlets distributes gas onto the top surface of the wafer to provide localized temperature control.

Abstract: A data holding control signal for each data line is supplied to a plurality of source followers that are connected together in parallel. The parallel-connected source followers are a combination of at least one first follower that is illuminated with laser light only once and at least one second follower that is illuminated twice. A width of the laser light illumination for crystallization is equal to a pitch of the source followers multiplied by an integer that is not less than 3.

Abstract: Disclosed is an exposure apparatus for printing, by exposure, a pattern of an original on a substrate, which includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a detection system having an optical system, wherein a portion of a light path of the detection system is disposed in a first space enclosed by the housing, and wherein at least another portion of the detection system including an electric element thereof is disposed in a second space outside the housing.

Abstract: A laser apparatus and methods are disclosed for synthesizing areas of wide-bandgap semiconductor substrates or thin films, including wide-bandgap semiconductors such as silicon carbide, aluminum nitride, gallium nitride and diamond to produce electronic devices and circuits such as integral electronic circuit and components thereof.

Abstract: A probe of a scanning probe microscope (SPM) having a field-effect transistor (FET) structure at the tip of the probe, and a method of fabricating the probe are provided. The SPM probe having a source, channel, and drain is formed by etching a single crystalline silicon substrate into a V-shaped groove and doping the etching sloping sides at one end of the V-shaped groove with impurities.

Abstract: The present invention is provided to manufacture a dual gate oxide film. According to the present invention, it is possible to obtain a high-quality NO gate oxide film for high voltage and a high-quality NO gate oxide film for low voltage where nitrogen is distributed uniformly in the entire oxide films by carrying out a rapid annealing process in an inert atmosphere after carrying out an NO annealing process in order to prevent a phenomenon that nitrogen is not distributed uniformly and segregated in a gate oxide film for high voltage due to application of the NO annealing process after forming a gate oxide film for low voltage.