Abstract: A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.

Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.

Abstract: A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.

Abstract: A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.

Abstract: A method of forming a buried dielectric collar around a trench and of forming a trench capacitor, the buried dielectric collar formed by: (a) forming the trench in a substrate; (b) forming a multilayer coating on sidewalls and a bottom of the trench; (c) removing a continuous band of the multilayer coating from the sidewalls a fixed distance from a top of the trench to expose a continuous band substrate in the sidewalls of the trench; (d) etching, in said exposed band of substrate, a lateral trench extending into said substrate in said sidewalls of said trench; and (e) filling the lateral trench with a dielectric material to form the buried dielectric collar. The trench capacitor is formed by filling the trench or its variants with polysilicon.

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A method of fabricating a deep trench capacitor is provided. A substrate with a deep trench thereon is provided. A bottom electrode is formed at a bottom of the deep trench and a capacitor dielectric layer, a first conductive layer, a protective layer and a collar layer are sequentially formed on the surface of the deep trench. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed, material is deposited into the deep trench to form a material layer. A portion of the material layer is removed to form a first opening. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed. A portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening. After removing the material layer, a second conductive layer and a third conductive layer are sequentially formed in the deep trench.

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract: Disclosed herein is a method of forming a nonvolatile memory device. The method comprises steps of forming a tunnel insulation pattern and a first floating gate pattern that are sequentially stacked on a semiconductor substrate, and then forming a trench comprising sidewalls aligned with the first floating gate pattern in the semiconductor substrate. Next, a device isolation layer is formed to fill in the trench, and an etch stop layer and a mold layer are sequentially formed on the device isolation layer and on the first floating gate pattern. The mold layer and the etch stop layer are successively patterned to form a groove exposing at least the first floating gate pattern, and a second floating gate pattern is formed to fill in the groove. This method can prevent bridges of floating gate layer that usually occur from regions not being fully etched due to high device integration.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

Abstract: A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching process is conducted to etch the substrate down to the doped region to form a shallow trench. Thereafter, an isolating material is filled into the shallow trench to form an STI layer. The doped region is located directly under the STI layer, and no doped region is formed in the sidewall of the shallow trench.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF4/SiF4/O2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C4F8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, forming an undensified conformal insulation layer on the surface such that, on account of the different radii of curvature, regions with different mechanical stress are produced in the insulation layer, and carrying out an etching-back to remove partial regions of the insulation layer in a manner dependent on the different mechanical stress in the insulation layer.

Abstract: A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this case, a precursor compound of a metal to be deposited is condensed out on the semiconductor surface and subsequently decomposed thermally. The method makes it possible to fill trenches with a high aspect ratio, it being possible to effectively suppress the formation of voids.

Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

Abstract: In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: A semiconductor device and method of making the same is provided having enhanced isolation between the bit line contact and the gate region of the semiconductor device. A gate conductor spacer and a recess fill material provide the enchanced isolation. The recess fill material substantially fills a recess defined by the gate conductor spacer and has a different composition than the gate conductor spacer.

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: The present invention provides a technology which allows the improvement of the capacitor capacitance per unit area, and a technology which allows the simplification of a manufacturing process associated therewith. At least not less than one capacitor formation trench causing the uneven surface is formed on the surface of a capacitor formation region. As a result, the surface area of a capacitor is increased, which enables the improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench formed in the surface of the semiconductor substrate are formed by the same step. As a result, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step.

Abstract: A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the cell-transistor and has the potential for increasing the node capacitance (like DRAM storage node).

Abstract: A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

Abstract: Oxynitridation processing for heat treating a substrate in an atmosphere containing NO (nitrogen monoxide) and ion implantation of nitrogen are used in combination to control the concentration of nitrogen introduced near the boundary between a gate oxide film and a substrate (well), in the order of higher concentration given as: n-channel MISFET having a thick gate oxide film>n-channel MISFET having a thin gate oxide film>p-channel MISFET having the thick gate oxide film, p-channel MISFET having the thin gate oxide film, with no additional use of photomasks, whereby reliability to hot carriers and reliability to NBT can be compatibilized by optimizing the concentration of nitrogen introduced to the boundary between the gate oxide films of four types of MISFET of different conduction type and different gate oxide film thickness and the substrate (well).

Abstract: An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolished to form a recessed conductive layer within the first dielectric layer.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.

Abstract: Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

Abstract: The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z).

Abstract: A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Abstract: The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact of the present invention, in conjunction with any DT top isolation approach, allows for an aggressive post GC etch treatment to avoid gate to bit line shorts without compromising the contact between the GC and the vertical gate.

Abstract: Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

Abstract: A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Abstract: A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each the deep trench capacitor construction having a collar construction and a conductor construction is provided. The method of forming a shallow trench includes steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions, which is not covered by the mask, so as to form a first depth trench, in which the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, in which the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.

Abstract: The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.

Abstract: A method and structure for forming a trench in a semiconductor substrate that includes a semiconductor material such as silicon. The method and structure may be used to form a deep trench or a shallow trench, without having a pad oxide in contact with the semiconductor substrate. The method for forming the deep trench forms a nitride layer on the semiconductor substrate, wherein the selectively etchable layer (e.g., a nitride layer) is selectively etchable with respect to the semiconductor substrate, and wherein there is no pad oxide between the selectively etchable layer and the semiconductor substrate. An erosion resistant layer (e.g., a hard mask oxide layer) is formed on the selectively etchable layer, wherein the erosion resistant layer is resistant to being etched by a reactive ion etch (RIE) process that etches the semiconductor substrate. Then the deep trench is formed by RIE through the erosion resistant layer, through the selectively etchable layer, and into the semiconductor substrate.

Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A process for forming air gap isolation regions between a bit line contact structure and adjacent capacitor structures, to reduce the capacitance of the space between these structures, has been developed. The process features the formation of insulator spacers on the sides of capacitor openings. After formation of capacitor structures, in the capacitor openings, top portions of the insulator spacers are exposed via a first selective etch procedure, allowing a second, selective, isotropic etch procedure to completely remove the insulator spacers creating the air gap isolation regions now located between the capacitor structure and an adjacent insulator layer. Subsequent deposition of an overlying insulator layer, comprised with poor conformality properties, allows coverage of the capacitor structures, however without filling the air gap isolation regions.

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract: A MOSFET device and method, the method involves forming the MOSFET device by selectively doping bordering channel regions in the device such that, in operation, the threshold, or turn-on, voltage is equalized across the channel. The device structure comprises a self-aligned channel edge implant region for equalizing threshold voltages in the channel edge region with threshold voltages in the channel interior region, thereby virtually eliminating sub-threshold leakage current in low voltage applications.

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device.

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device.