Abstract: A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.

Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

Abstract: A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming a first insulating layer and a second insulating layer on a region of a substrate excluding an inactive region thereof; forming a trench of the inactive region of the substrate by using the first and second insulating layers as a mask; forming an element isolation layer in the trench; and removing the first insulating layer and the second insulating layer and, at the same time, removing a predetermined thickness of the element isolation layer.

Abstract: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region; forming a groove portion in the element separation structure forming region; forming a groove portion oxide film in the groove portion; forming a pre-filling oxide film for filling the groove portion; removing the pre-filling oxide film; forming a resist layer on the silicon nitride film and the pre-filling oxide film; forming a resist mask on the element separation structure forming region; removing the silicon nitride film and the first thermal oxide film; forming a second thermal oxide film on the substrate; and removing the second thermal oxide film and leveling the pre-filling oxide film to form a filling portion.

Abstract: A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 ? to 1000 ? or greater, the etching process partially removes the active layer. The remaining active layer is oxidized prior to a wet dip for removing the mask layer, preventing the wet dip process from undercutting the active region. When the active layer of the SOI wafer is relatively thin, such as about 25 ? to 400 ?, the partial etching step may be reduced or eliminated. In this case, the active layer is oxidized with little or no etching of the active layer. The exposed active layer is oxidized to prevent the wet dip process from undercutting the active region.

Abstract: A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500° C. in an oxidizing environment. The method includes the following three principal operations: exposing a substrate surface to an aluminum-containing precursor gas to form a substantially saturated layer of aluminum-containing precursor on the substrate surface; exposing the substrate surface to a silicon-containing precursor gas to form the dielectric film; and annealing the dielectric film in a low temperature oxygen-containing high density plasma. The resulting film has improved mechanical properties, including minimized seams, improved WERR, and low intrinsic stress, comparable to a high temperature annealing process (˜800° C.), but without exceeding the thermal budget limitations of advanced devices.

Abstract: According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

Abstract: Particle migration, such as silver electro-migration, on a flat ceramic surface is effectively eliminated by an upward vertical barrier formed on the surface or a groove formed in the surface between two silver conductors.

Abstract: To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.

Abstract: Dendron ligands or other branched ligands with cross-linkable groups were coordinated to colloidal inorganic nanoparticles, including nanocrystals, and substantially globally cross-linked through different strategies, such as ring-closing metathesis (RCM), dendrimer-bridging methods, and the like. This global cross-linking reaction sealed each nanocrystal within a dendron box to yield box-nanocrystals which showed dramatically enhanced stability against chemical, photochemical and thermal treatments in comparison to the non-cross-linked dendron-nanocrystals. Empty dendron boxes possessing a very narrow size distribution were formed by the dissolution of the inorganic nanocrystals contained therein upon acid or other etching treatments.

Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.

Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Abstract: The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising material sidewalls within the isolation trenches. Electrically insulative trench isolation material is formed within the isolation trenches over the epitaxially-grown silicon-comprising layer. Other aspects and implementations are contemplated.

Abstract: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume the silicon overlying the insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon, and so is applicable to SOI as well as conventional semiconductor substrates.

Abstract: Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided.

Abstract: A method of operating a substrate processing chamber comprising transferring a first substrate into the substrate processing chamber and heating the substrate to a first temperature of at least 510° C.; depositing an insulating layer over the first substrate while reducing the temperature of the substrate from the first temperature to a second temperature that is lower than the first temperature; transferring the first substrate out of the substrate processing chamber; removing unwanted deposition material formed on interior surfaces of the chamber during the depositing step by introducing reactive halogen species into the chamber while increasing the temperature of chamber; transferring a second substrate into the substrate processing chamber and heating the substrate to the first temperature; and depositing an insulating layer over the second substrate while reducing the temperature of the substrate from the first temperature to the second temperature.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second oxide layers are etched such that the first oxide layer is wholly removed and the second oxide layer remains only on the first silicon epitaxial layer. A third oxide layer is thermally grown on entire resultant surfaces and then blanket-etched to remain only on sidewalls of the first silicon epitaxial layer. A second silicon epitaxial layer is grown on the exposed substrate between the first active regions, thus forming second active regions. The second oxide layer remaining on the first silicon epitaxial layer is removed. The first and second active regions are separated and electrically isolated by the third oxide layer.

Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. The process of creating the polarizable layer comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5–50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25–300 degrees Celsius. An annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: A method for processing a substrate to produce a structure, for example an insulating trench, uses a lithographic mask exposure process. Conventionally, the optical resolution limit prescribes the minimum width for any structure that can be produced. The method produces structures having a width less than the optical resolution limit on raised regions of the semiconductor substrate. Use is made of spacer technology, before the application of which the method first involves the local level ratios on the semiconductor substrate being reversed by trench etching, trench filling and subsequent back-etching of the trench interspace. The method allows insulating trenches of any narrow width between zero and the respective optical resolution limit to be produced on locally raised surface regions of the substrate.

Abstract: There is disclosed a method of producing an SOI wafer in which an SOI layer is formed on a buried oxide film by, at least implanting at least one kind of ion of hydrogen ion and a rare gas ion into the surface portion of a bond wafer to form an ion-implanted layer, bonding the bond wafer and a base wafer to each other through an oxide film, and delaminating the resultant bonded wafer at the ion-implanted layer, wherein assuming that X [nm] represents the thickness of the buried oxide film and Y [nm] represents the thickness of the SOI layer in the SOI wafer immediately after delaminating at the ion-implanted layer, when the thickness X of the buried oxide film is X?100, in forming the ion-implanted layer, the ion implantation is carried out with the ion implantation conditions being set such that the sum X+Y of the thickness of the buried oxide film and the thickness of the SOI layer satisfies X+Y>1500?14X, after which the bonding process and the delaminating process are carried out and, thereafter, a thin

Abstract: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.

Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies.

Abstract: Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

Abstract: A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

Abstract: The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The dopants are doped in a manner to allow the conductive layer to have different doping distributions with respect to a thickness. Particularly, the dopants are doped until reaching a target deposition thickness by gradually increasing a concentration of the dopants from a first concentration to a second concentration for an interval from an initial deposition of the conductive layer to the target deposition thickness, and the second concentration is consistently maintained throughout for an interval from the target deposition thickness to a complete deposition thickness.

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

Abstract: The present invention discloses method for manufacturing alignment mark wherein a predetermined thickness of a device isolation film is etched prior to removing a pad nitride film during a shallow trench isolation process to increase contrast. In accordance with the method, a pad nitride film pattern and a pad oxide film pattern exposing a predetermined portion of the semiconductor substrate are formed. The semiconductor substrate is etched using the pad nitride film pattern as a mask to form an alignment mark trench. A device isolation film is formed in the trench and a predetermined thickness of the device isolation film is etched to form an alignment mark. The pad nitride film pattern is then removed.

Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

Abstract: High density plasma chemical vapor deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots are provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. The etch back part of the process involves an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality gap fill operations.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.

Abstract: A method of filling intervals between protruding structures is provided. A substrate with a plurality of protruding structures thereon is provided. The protruding structures are distributed over the substrate such that intervals are formed between adjacent protruding structures. A first dielectric layer is formed over the substrate so that the dielectric material fills the intervals between the protruding structures and covers the protruding structures as well. The first dielectric layer has a plurality of apertures therein located at a level above a top section of the protruding structures. A chemical/mechanical polishing operation is performed to remove a portion of the dielectric layer and expose the apertures to form a plurality of openings. An anisotropic etching operation is performed to increase the width of these openings. Finally, a second dielectric layer is formed over the first dielectric layer to fill the openings completely.

Abstract: DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

Abstract: A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region.

Abstract: In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Abstract: An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment mark structure (22) is provided. The features of the alignment mark structure (22) are formed in an alignment mark region (20) concurrently while features for a circuit region having vertical gate transistors are being formed. There are no extra or added processing steps added for forming the alignment mark structure (22) because it is formed concurrently while forming features in the circuit region. The resulting alignment mark structure (22) has step features (62) so that the step features (62) can be seen after the opaque material layer (88) covers the alignment mark structure (22).

Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.

Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.