Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: A substrate is provided, and a dielectric layer is formed, thereon. Then a photoresist layer is formed on the dielectric layer and defined a predetermined region for ion implantation. Next, a dense region of dielectric layer is formed by retrograde implantation with photoresist layer as an ion implanted mask, wherein the dense region is a predetermined region for trench. A hard mask layer is formed on the dielectric layer after the photoresist layer is removed. Afterward forming and defining another photoresist layer on the hard mask layer to expose a partial surface of the hard mask layer as a trench region, wherein the partial surface of the hard mask layer comprises the dense region. Subsequently, an etching process is performed by means of the photoresist layer as the etched mask to etch through the hard mask layer and the dielectric layer until the substrate surface is exposed for patterning the dual damascene.

Abstract: A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within a first depth zone through the second portions of the substrate. The first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth. The substrate is annealed for a first time to form a noncontiguous buried insulating layer substantially within the first depth zone in the second portions of the substrate. The substrate is masked with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate. The fourth portions of the substrate at least partially overlap the second portions of the substrate. A second dopant is implanted substantially within a second depth zone through the fourth portions of the substrate.

Abstract: There is provided a semiconductor apparatus, and a fabrication method thereof, which are improved such that a reduction in concentration at the SOI active layer is prevented, and a parasitic MOSFET is not formed even in cases where Mesa-type isolation techniques and the STI isolation method are applied to form a MOSFET in an SOI layer. In an isolation step for separating and forming a plurality of device regions, a layered film of a nitride film (Si3N4) and an oxide film (SiO2) is taken as an isolation mask, and a semiconductor layer (SOI layer) is removed from the isolation region by etching. Subsequently, a SiON film (7) is formed on a sidewall surface of an SOI layer (3) by a nitridation oxidation process. Thereafter, isolation is performed by the STI method. Finally, an oxide film (9) and an electrode (10) are formed, and a MOSFET is completed.

Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.

Abstract: A method for fabricating ultra-thin single-crystal metal oxide wave retarder plates, such as a zeroth-order X-cut single-crystal LiNbO3 half-wave plate, comprises ion implanting a bulk birefringent metal oxide crystal at normal incidence through a planar major surface thereof to form a damage layer at a predetermined distance d below the planar major surface, and detaching a single-crystal wave retarder plate from the bulk crystal by either chemically etching away the damage layer or by subjecting the bulk crystal having the damage layer to a rapid temperature increase to effect thermally induced snap-off detachment of the wave retarder plate. The detached wave retarder plate has a predetermined thickness d dependent on the ion implantation energy.

Abstract: A method for estimating molecular nitrogen implantation dosage. The semiconductor wafers are first implanted with various concentration of molecular nitrogen. After implantation, the implanted wafers and a non-implanted wafer are subjected to thermal process to grow oxide layer. The thickness of oxide layer on the wafers with various implantation dosage is measured. Because implanted nitrogen on the wafers suppresses the growth of oxide layer, a suppression ratio is computed from the difference in thickness of the oxide layer between the implanted and non-implanted semiconductor wafers to stand for the thickness variation. Then, a relation between the suppression ratio and the dosages of molecular nitrogen is built. A molecular nitrogen dosage needed to grow a predetermined thickness of oxide layer on a process wafer is computed by inputting the predetermined thickness into the relation.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form a first implant region of the first ions in the Si-containing substrate. Following the implantation of first ions, a first annealing step is performed which forms a buried semi-insulating or insulating region within the Si-containing substrate. Next, second ions that are insoluble in the semi-insulating or insulating region are selectively implanted into portions of the buried semi-insulating or insulating region. After the selective implant step, a second annealing step is performed which recrystallizes the buried semi-insulating or insulating region that includes second ions to the same crystal structure as the original Si-containing substrate.

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Abstract: A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130, of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.

Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: Methods of producing buried insulating layers in semiconductor substrates are disclosed whereby a dose of selected ions is implanted into a substrate to form a buried precursor layer below an upper layer of the substrate, followed by oxidation of the substrate in an atmosphere having a selected oxygen concentration to form an oxide surface layer. The oxidation is performed at a temperature and for a time duration such that the formation of the oxide layer causes the injection of a controlled number of atoms of the substrate from a region proximate to an interface between the newly formed oxide layer and the substrate into the upper regions of the substrate to reduce strain. A high temperature annealing step is then performed to produce the insulating layer within the precursor layer.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.

Abstract: This invention concerns a process of forming a polarizable layer in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. This process comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5-50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25-300 degrees Celsius. After implantation, an annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: A semiconductor-on-insulator (SOI) chip. The SOI chip having a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first tile and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness; wherein the BOX layer is formed under the active layer in an area of the first tile by implanting oxygen ions with a first energy level and a first dosage and the BOX layer is formed under the active layer in an area of the second tile by implanting oxygen ions with a second energy level and a second dosage.

Abstract: A method of forming thin film waveguide regions in lithium niobate uses an ion implant process to create an etch stop at a predetermined distance below the lithium niobate surface. Subsequent to the ion implantation, a heat treatment process is used to modify the etch rate of the implanted layer to be in the range of about 20 times slower than the bulk lithium niobate material. A conventional etch process (such as a wet chemical etch) can then be used to remove the virgin substrate material and will naturally stop when the implanted material is reached. By driving the ions only a shallow distance into the substrate, a backside etch can be used to remove most of the lithium niobate material and thus form an extremely thin film waveguide that is defined by the depth of the ion implant. Other structural features (e.g., ridge waveguides) may also be formed using this method.

Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.

Abstract: Gettering layers are formed near element isolation insulating films in an active layer on a buried oxide film. The gettering layers trap mainly heavy metals diffused from the element isolation insulating films into the active layer.

Abstract: A method of glass frit bonding wafers to form a package, in which the width of the glass bond line between the wafers is minimized to reduce package size. The method entails the use of a glass frit material containing a particulate filler material that establishes the stand-off distance between wafers, instead of relying on discrete structural features on one of the wafers dedicated to this function. In addition, the amount of glass frit material used to form the glass bond line between wafers is reduced to such levels as to reduce the width of the glass bond line, allowing the overall size of the package to be minimized. To accommodate the variability associated with screening processes when low volume lines of paste are printed, the invention further entails the use of storage regions defined by walls adjacent the glass bond line to accommodate excess glass frit material without significantly increasing the width of the bond line.

Abstract: A method for forming an isolation region in a semiconductor device, in which nitrogen ions are injected into a region of an isolation oxide film to form an oxynitride film, thereby preventing formation of a recess at a top edge of the isolation oxide film, which improves the device isolation characteristic. The method includes depositing a pad oxide film and a pad nitride film over a substrate. The pad oxide film, the pad nitride film, and the substrate are selectively removed to form a trench, which is then filled with an isolation oxide film. Nitrogen ions are injected into an entire surface of the pad nitride film, inclusive of the isolation oxide film, to form an oxynitride film in a region of the isolation oxide film. The pad nitride film and the pad oxide film are removed, and a gate oxide film and a polysilicon layer are deposited.

Abstract: A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.

Abstract: A semiconductor and a method of manufacturing thereof form a region with a sufficient gettering effect. A p-type channel MOSFET and an n-type channel MOSFET are formed in an n-type semiconductor layer, which is isolated in a form of islands on an SOI substrate. A high-concentration impurity diffused region is formed in such a manner as to surround the p-type channel MOSFET and the n-type channel MOSFET. The high-concentration impurity diffused region has a surface concentration of between 1×1018 atoms/cm−3 and 5×1020 atoms/cm−3 for achieving a desired gettering effect.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: A semiconductor device having a substrate, an insulating film formed in the substrate, a conductive layer formed on the insulating film and having at least a part in contact with the insulating film made of a conductive material having a work function near a substantial center of an energy band gap of the substrate material and containing a predetermined amount of impurity, and a takeout electrode formed in the substrate and a method for producing the same.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing substrate; and annealing the Si-containing substrate containing the implanted oxygen ion at a temperature of about 1300° C. or above and in a chlorine-containing ambient so as to form a buried oxide region that electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. The chlorine-containing ambient employed in the annealing step includes oxygen and a chlorine-containing carrier gas such as HCl, methylene chloride, trichloroethylene and trans 1,2-dichloroethane.

Abstract: Methods and apparatus are provided for forming ultrashallow junctions in semiconductor wafers. The method includes the step of introducing into a shallow surface layer of a semiconductor wafer a dopant material that is selected to form charge carrier complexes, such as exciton complexes, which produce at least two charge carriers per complex. The semiconductor wafer containing the dopant material may be processed, such as by thermal processing, to form the charge carrier complexes. The charge carrier complexes are interstitial and therefore are not subject to the limitations imposed by the electrical solubility limits resulting from incorporation into substitutional sites. Thus, low sheet resistance can be obtained.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: A method for forming a semiconductor devices structure includes providing a semiconductor substrate, forming a deep trench continuously in the substrate to separate a first region from a second region, and then forming a silicon-on-insulator region in the first region while maintaining a non-silicon-on-insulator region in the second region. The deep trench has a depth which is at least as deep as the depth of the buried oxide in the substrate. The invention also includes a device structure resulting from the method.

Abstract: Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 &mgr;m or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.

Abstract: Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.

Abstract: A method of substantially reducing charge build-up in a SOI device is provided. The method includes depositing a dielectric material on a surface of a semiconductor structure which includes at least silicon-on-insulator (SOI) devices therein. Next, a first conductive material is deposited on the dielectric material and then holes are drilled through the conductive material and the dielectric insulating material. Each hole is filled with a second conductive material, and thereafter selective portions of the first conductive material are removed to form contact pads for further probing. The method is especially useful in focused ion beam (FIB) drilling.

Abstract: A monocrystalline silicon substrate is subjected to the following operations: implantation of doping impurities in a high concentration to form a planar region of a first type; selective anisotropic etching in order to hollow out trenches to a depth greater than the depth of the planar region; oxidation of the silicon inside the trenches, starting a certain distance from the surface of the substrate, until a silicon dioxide plaque is formed, surmounted by residues of strongly-doped silicon; epitaxial growth between and on top of the silicon residues to close the trenches and to bring about a redistribution of the doping impurities into the silicon grown to produce a buried region with low resistivity in an epitaxial layer of high resistivity.

Abstract: Smaller active regions are enabled by forming nickel suicide extensions from the nickel silicide layers on the source/drain regions and landing contacts on the nickel silicide extensions. The nickel silicide extensions are formed by implanting Si ions in the field oxide areas adjacent to the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a nickel silicide layer that extends from the source/drain regions onto the Si-implanted field oxide areas. In an embodiment of the present invention, the nickel silicide is NiSi.

Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. At least parts of the buried insulator layer include a nitrided semiconductor oxide. The nitrided semiconductor oxide may be formed by means of a nitride implant with sufficient energy to pass through a surface semiconductor layer and penetrate into a buried oxide layer. Following the nitride implant the device may be annealed to remove damage to the surface semiconductor layer, as well as to form a high quality nitrided oxide in the buried insulator layer. The nitrided semiconductor oxide material may reduce or prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: A technique for fabricating substrates such as a silicon-on-insulator substrate using a plasma immersion ion implantation (“PIII”) system 10. The technique includes a method, which has a step of providing a substrate 2100. Ions are implanted 2109 into a surface of the substrate to a first desired depth to provide a first distribution of the ions using a plasma immersion ion implantation system 10. The implanted ions define a first thickness of material 2101 above the implant. Global energy is then increased of the substrate to initiate a cleaving action, where the cleaving action is sufficient to completely free the thickness of material from a remaining portion of the substrate. By way of the PIII system, the ions are introduced into the substrate in an efficient and cost effective manner.

Abstract: Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

Abstract: An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.