Abstract: For fabricating a field effect transistor in SOI (semiconductor on insulator) technology, an opening is etched through a first surface of a first semiconductor substrate, and a dielectric material is deposited to fill the opening. The dielectric material and the first surface of the first semiconductor substrate are polished down to form a dielectric island comprised of the dielectric material surrounded by the first surface of the first semiconductor substrate that is exposed. The semiconductor material of the first semiconductor substrate remains on the dielectric island toward a second surface of the first semiconductor substrate. A layer of dielectric material is deposited on a second semiconductor substrate. The first surface of the first semiconductor substrate is placed on the layer of dielectric material of the second semiconductor substrate such that the dielectric island and the first surface of the first semiconductor substrate are bonded to the layer of dielectric material.

Abstract: A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.

Abstract: A process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate from thermally oxidized silicon wafer so that processing temperatures are limited to 900° C. is disclosed. The substrate is fabricated using H2 split process. Processing temperatures are limited to temperature of initiating of out-diffusion of oxygen from silicon dioxide into silicon. The limit prevents deterioration of buried oxide, and the oxide has low hole trap density that is equal to the trap density of an initial thermal silicon dioxide. Processing temperatures after implantation for H2 split process are limited to temperature of stability of dislocation microloops induced by the implantation at its damage peak. Resulting SOI structure have a gettering layer made from the microloops. The getter prevents yield drop caused by heavy metal contamination during the fabrication. Finished SOI devices have improved gate oxide integrity.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide thickness. This in turn enhances the performance of MOSFET devices formed thereon. The nitrogen enrichment is accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, approaching that of silicon nitride which not only decreases it's effective thickness with respect to gate capacitance, but also lowers device leakage by suppressing hot carrier injection over device drain regions.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A transistor structure having dimensions below about 100 nm is provided. The transistor structure comprises a substrate with a first polarity. The substrate includes a shallow halo implant having the first polarity defined at a first depth within the substrate. The substrate also has a deep halo implant which is the same polarity as the substrate and is defined to a second depth deeper than the first depth of the shallow halo implant. The shallow halo implant and the deep halo implant allow a peak concentration of substrate impurities at a level below the gate such that the resistance of the transistor is minimized along with the threshold voltage, short channel effects and leakage current in the transistor.

Abstract: This invention discloses a method for fabricating SOI material, incorporating an amorphous process introduced by ion implantation in the conventional SIMOX methods, which enhances diffusion of various atoms in the amorphous region in annealing process. It realizes under a lower temperature annealing to eliminate threading dislocations and other crystal defects in the top silicon layer and silicon islands, pinholes and other silicon segregation products in the buried oxide layer and fabricate high quality of SOI material. Another method for forming SOI material is also described, incorporating an amorphous process introduced by ion implantation in the SIMNI or SIMON methods. It forms amorphous buried nitride or oxynitride layer, a top single crystal silicon layer and a sharp interface between the top layer and the buried layer.

Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.

Abstract: There is disclosed a method of fabricating an SOI wafer in which a bond wafer to form a SOI layer and a base wafer to be a supporting substrate are prepared; an oxide film is formed on at least the bond wafer; hydrogen ions or rare gas ions are implanted in the bond wafer via the oxide film in order to form a fine bubble layer (enclosed layer) within the bond wafer; the ion-implanted surface is brought into close contact with the surface of the base wafer; and then heat treatment is performed to separate a thin film from the bond wafer with using the fine bubble layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and wherein deviation in the thickness of the oxide film formed on the bond wafer is controlled to be smaller than the deviation in the ion implantation depth, and the SOI wafer fabricated thereby. There is provided an SOI wafer which has an SOI layer having improved thickness uniformity.

Abstract: A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: A method for making a ULSI MOSFET using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.

Abstract: The invention relates to a method of producing a thin layer of semiconductor material including:

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A method for processing a semiconductor wafer transforms the wafer into one which has a plurality of surface semiconductor platforms for formation of integrated circuit elements thereupon. The platforms are connected to a subsurface bulk layer of semiconductor material via integrally-formed bridges of semiconductor material. The platforms are otherwise surrounded with an electrically-insulating material, thereby providing good insulation between adjacent of the platforms. The method includes the steps of placing a mask on a wafer surface of the wafer, forming a subsurface altered material beneath portions of the wafer surface not covered by the mask, creating exposure openings through the wafer surface to expose a portion of the subsurface altered material, selectively removing the subsurface altered material by selective etching, and filling the subsurface regions and the exposure openings with an electrically-insulating material. In an exemplary embodiment the mask includes a plurality of gate conductors.

Abstract: A method of fabricating a shallow trench isolation includes formation of a polishing stop layer. The polishing stop layer is formed in a fill material by performing ion implantation to implant atoms in the fill material. The depth of the polishing stop layer can be controlled by the energy of the implanted atoms. The polishing stop layer prevents the fill material from being dished by chemical-mechanical polishing. The polishing stop layer also prevents scratches from forming in the surface of the fill material, which is used to form isolation regions.

Abstract: A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interact with the Silicon matrix of the substrate to establish field isolation areas that extend deeper than the buried oxide layer of the SOI device, to ensure adequate component isolation.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: A process for separating at least two elements of a structure. The two elements are in contact with one another along an interface and are fixed to one another by interatomic bonds at their interface. An ion implantation is performed in order to introduce ions into the structure with an adequate energy for them to reach the interface and with an adequate dose to break the interatomic bonds. This brings about at the interface, the formation of a gaseous phase having an adequate pressure to permit the separation of the two elements.

Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source.

Abstract: An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device.

Abstract: The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the silicon wires has a pair of ends. Oxynitride layers covers on the silicon wires. A polysilicon layer covers the oxynitride layers and the buried oxide layer. A source region and a drain region connect to a first end and a second end of each of the silicon wires, respectively.

Abstract: A method for making a thin film of solid material, including bombarding one face of a substrate of the solid material with at least one of rare gas ions and hydrogen gas ions so as to create a layer of microcavities seperating the substrate into two regions at a depth neighboring the average ion penetration depth, and heating the layer of microcavities to a temperature sufficient to bring about a separation between the two regions of the substrate. The solid material includes one of a dielectric material, a conducting material, a semi-insulating material, and an unorganized semiconducting material.

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving the steps of providing a monocrystalline silicon substrate; patterning a mask over the monocrystalline silicon substrate thereby exposing a portion of the monocrystalline silicon substrate; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon substrate; removing the mask from the monocrystalline silicon substrate; implanting a second dosage of oxygen atoms without using an implantation mask in the monocrystalline silicon substrate; and annealing the oxygen implanted monocrystalline silicon substrate to provide the Silicon-on-Insulator substrate.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: A process for forming high density isolation for very large scale integration on semiconductor chips, comprising the steps of: orientation-dependent etching a portion of a semiconductor substrate to form protruding features on a surface of the semiconductor substrate; forming a layer of insulation above the etched portion of the semiconductor substrate; implanting atoms and/or ions of a non-conductive material to a first predetermined depth into the insulation layer and a second predetermined depth into the protruding features in the semiconductor substrate to provide a detectible change in material characteristic at that depth; and polishing the insulation layer and protruding features down to a depth determined by detecting the change in material characteristic to thereby remove a top portion of the protruding features to form a first surface on each of a plurality of the protruding features.

Abstract: In a method of fabricating an SOI wafer, an oxide film is formed on the surface of at least one of two silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form a fine bubble layer (enclosed layer) within the wafer; the ion-implanted silicon wafer is superposed on the other silicon wafer such that the ion-implanted surface comes into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed in order to delaminate a portion of the ion-implanted wafer while the fine bubble layer is used as a delaminating plane, in order to form a thin film to thereby obtain an SOI wafer. In the method, a defect layer at the delaminated surface of the thus-obtained SOI wafer is removed to a depth of 200 nm or more through vapor-phase etching, and then mirror polishing is performed. Therefore, the obtained SOI wafer has an extremely low level of defects and a high thickness uniformity.

Abstract: A process for thin film formation is provided which comprises a step of separation of a substrate constituted of a nonporous Si layer, a porous Si layer formed thereon, and a less porous Si layer formed further thereon into the nonporous Si layer and the less porous Si layer at the porous Si layer, wherein the separation is caused by projecting a laser beam through the side face of the substrate. From the separated substrate, an SOI substrate is prepared, and the non porous Si layer is recycled to the SOI substrate production process. This SOI substrate production process saves the consumption of the material and lowers the production cost. The substrates are separated definitely. A process for producing a photoelectric transducing apparatus such as solar cells with material saving and low cost is also provided in which the porous layer is separated definitely without strong adhesion between the substrate and a jig.

Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures.

Abstract: A semiconductor fabrication process uses a buried, oxygen-rich layer as a stop etch in a trench isolation area, with minimal masking. According to one embodiment, the process involves applying a mask to protect selected portions of a silicon-based substrate, and then using the mask to implant an oxygen-based substance into unmasked portions of the substrate, thereby forming a buried oxygen layer at a selected depth within the substrate. The same mask is then used in an etching process to form the desired trench structure. The depth of the trench is defined as a result of terminating the etch process upon reaching the buried oxygen layer.

Abstract: First, oxygen ions of a high concentration are implanted into a silicon substrate 1, by which a high-concentration oxygen implanted layer 3 is formed. Subsequently, a heat treatment for about 4 hours at 1350.degree. C. is carried out in an atmosphere of Ar with a 0.5% concentration oxygen for the formation of a buried oxide layer 5. Next, pulse laser annealing is performed for melting and recrystallization of the surface silicon layer. Pulsed laser beam is radiated at an energy density of 1200 mJ/cm.sup.2 or more. The pulsed laser beam is able to melt the semiconductor surface in several 10's nsec by virtue of its extremely large power density in irradiation of 10.sup.7 W/cm.sup.2. By iterating this pulse laser annealing, the surface silicon layer iterates to melt and recrystallize, activating the activities of crystal defects, by which damage recovery based on crystal seeds is accomplished.

Abstract: Disclosed are an isolation film of a semiconductor device and a method for fabricating the same, which prevent the isolation film from being damaged due to misalignment when forming a contact hole in a region adjacent to the isolation film, to ensure stable effective isolation distance. The isolation film of a semiconductor device includes a semiconductor substrate, a lower isolation film formed in the semiconductor substrate, and an upper isolation film formed on the lower isolation film, with a material having etching selectivity different from the lower isolation film.

Abstract: A layer of silicon oxide is first formed on the silicon substrate. A mask is then formed on the oxide layer to define at least one surface region of the oxide that is not covered by the mask and a continuous strip of mask material that extends continuously around the unmasked oxide surface region. The mask is then used to etch the oxide surface region to expose an underlying substrate surface region and, thereby creating a continuous wall of oxide around the substrate surface region. The mask is then removed and oxygen ions are implanted into the silicon substrate to define a horizontal layer of oxide ions within the substrate. The wall of oxide surrounding the substrate surface region impairs the implant of oxygen ions beneath the wall such that a continuous substantially vertical wall of oxygen ions is formed in the substrate extending from the perimeter of the horizontal oxygen ion layer to the surface of the substrate.

Abstract: The radiation hardness of a microelectronic device is improved by implant dopant ions, such as Si, into an oxide layer. This implantation creates electron traps/recombination centers in the oxide layer. A subsequent anneal remove defects in the active silicon layer.

Abstract: An object of the present invention is to provide a technology of reducing a nickel element in the silicon film which is crystallized by using nickel. An extremely small amount of nickel is introduced into an amorphous silicon film which is formed on the glass substrate. Then this amorphous silicon film is crystallized by heating. At this time, the nickel element remains in the crystallized silicon film. Then an amorphous silicon film is formed on the surface of the silicon film crystallized with the action of nickel. Then the amorphous silicon film is further heat treated. By carrying out this heat treatment, the nickel element is dispersed from the crystallized silicon film into the amorphous silicon film with the result that the nickel density in the crystallized silicon film is lowered.

Abstract: A method of fabricating layered integrated circuits on a silicon wafer utilizes the buried oxide insulating layer of a SOI structure for isolating junction devices such as diodes, well resistors, N.sup.30 resistors, P.sup.30 resistors, and bipolar junction transistors from MOS transistors. Consequently, junction devices are formed in the semiconductor substrate below the buried oxide insulation layer while the MOS transistors are formed in an epitaxial silicon layer above the buried oxide insulation layer. Furthermore, the MOS transistors located above the epitaxial silicon layer are isolated from each other by trench isolation structures. Since this invention provides a method of fabricating a layered integrated circuit structure whose devices can be stacked on top of each other in separate layers, the degree of integration for each unit area of wafer surface is increased.

Abstract: A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions.

Abstract: A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.

Abstract: The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.

Abstract: A modified LOCOS isolation process for semiconductor devices is disclosed. First, a shielding layer is formed overlying a semiconductor substrate. The shielding layer is then patterned to form an opening that exposes a portion of the semiconductor substrate for forming a device isolation region. Next, oxygen ions are implanted with a tilt angle into the semiconductor substrate to form a doped region extending to the area under the margin of the shielding layer. A thermal oxidation process is then performed to form a field oxide layer on the semiconductor substrate. Since the oxidation rate of the area under the margin of the shielding layer is increased by the implanted oxygen ions, the bird's beak effect shown in conventional LOCOS process can be eliminated. After that, the shielding layer is removed to complete the fabricating process of this invention.

Abstract: Phosphorous ion is implanted into an SOI substrate under the conditions that the concentration is maximized in the upper silicon layer of the SOI substrate so as to forming a heavily-doped damaged layer, and the heavily-doped damaged layer is partially cured through a lamp annealing so as to concurrently form a heavily-doped buried layer and a gettering site layer.

Abstract: The method of the present invention is a method of including forming an oxide layer on the substrate. A nitride layer is subsequently formed on the oxide layer. A photoresist layer is formed on the nitride layer to define isolation regions that uncovered by the photoresist layer. A liquid phase deposition oxide is deposited on the isolation regions. Then the photoresist layer is removed. After removing the photoresist layer, an oxygen ion implantation is performed through the oxide layer and the nitride layer into the substrate by using the liquid phase deposition oxide layer as implant mask to form relative high oxygen ion contained regions in the substrate. After the ion implantation is done, the liquid phase deposition oxide layer is removed. An annealing process is carried out to form isolation regions in the substrate and recover implant-induced damage.

Abstract: A method of manufacturing a semiconductor device having a region which is partially thinner than the rest thereof is disclosed. A semiconductor thin layer is formed on an insulating layer by an annealing treatment after implanting ions into the semiconductor substrate at a predetermined depth. A semiconductor material is formed by epitaxial growing to a predetermined thickness on the semiconductor thin layer. The the insulating layer or eliminating the insulating layer and a part of the semiconductor substrate under the insulating layer is eliminated by an etching operation.

Abstract: A method for inserting a gaseous phase in a sealed cavity including inserting ions in the sealed cavity by ion implantation carried out at an energy level sufficient for the inserted ions to reach the sealed cavity and to form a gas having a gas pressure which deforms a wall of the sealed cavity. The ion implantation is performed using hydrogen ions, or a rare gas ions, such as helium ions. The method may be implemented into a method for manufacturing a structure with a soft electrical contact, a capacitor, or a matrix of pressure sensors.

Abstract: According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.