Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.

Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Abstract: A method of fabricating an isolation structure of a semiconductor device includes the following steps. Firstly, a substrate including a first surface and a second surface is provided. At least one trench is formed in the first surface of the substrate. The trench has a sidewall and a bottom surface. Then, a first chemical vapor deposition process is performed to form a first isolation layer on the first surface of the substrate and the sidewall and the bottom surface of the trench. Then, an anisotropic surface treatment process is performed, so that a surface of the first isolation layer has differential surface chemical properties. Afterwards, a second chemical vapor deposition process is performed to form a second isolation layer on the first isolation layer with a surface having differential surface chemical properties.

Abstract: A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well.

Abstract: An improved bulk FinFET with a punchthrough stopper region, and method of fabrication are disclosed. The dopants used to form the punchthrough stopper are supplied from a shallow trench isolation liner. An anneal diffuses the dopants from the shallow trench isolation liner into the bulk substrate and lower portion of the fins, to form the punchthrough stopper region.

Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

Abstract: A manufacturing method for the nodes of the RAM device, includes the steps as follows: forming a STI layer on a substrate to divide the substrate into several active areas; sequentially forming a first insulating layer and a hard mask layer on the substrate; etching the first insulating layer to form a first hole for exposing the STI layer and partial of the active areas; filling a conductive material in the first hole to form a conductor; forming a protective layer on the top surface of the conductor, wherein each protective layer has an opening aligning the STI layer; etching the conductor from the opening until the STI layer to form a second hole for exposing the STI layer, wherein each conductor is divided into two nodes by the second hole arranged therebetween; and forming a second insulating layer in the second hole for electrically isolating the nodes.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and after the forming the STI regions, oxidizing an upper portion of a semiconductor strip between the STI regions. A width of the upper portion of the semiconductor strip is reduced by the oxidizing. The STI regions are recessed, until a portion of the upper portion of the semiconductor strip is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

Abstract: A method for fabricating a deep trench isolation structure, wherein the method comprising steps as follows: A first hard mask layer, a second hard mask layer and a third hard mask layer are firstly formed in sequence on a substrate. The third hard mask layer is then patterned using the second hard mask layer as an etching stop layer. Subsequently, a trench etching process is performed using the patterned third hard mask layer as a mask to form a deep trench in the substrate.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.

Abstract: A method of fabricating a semiconductor device comprises forming a plurality of trenches in a bulk semiconductor substrate, each trench defining a semiconductor fin. A local dielectric material is deposited entirely on the semiconductor device and in the trenches to cover each semiconductor fin. The local dielectric material disposed in each trench is recessed a predetermined distance below the semiconductor fins. An etch resistant layer, which is resistant to at least one of a gate etching process and a spacer etching process, is formed on an upper surface of each recessed local dielectric material.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

Abstract: A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.

Abstract: According to one embodiment, a semiconductor storage device includes a first insulating film formed on a substrate and functioning as a FN (Fowler-Nordheim) tunnel film, a first floating gate formed on the first insulating film, an inter-floating-gate insulating layer formed on the first floating gate and functioning as a FN tunnel film, a second floating gate formed on the inter-floating-gate insulating layer, a second insulating film formed on the second floating gate, and a control gate formed on the second insulating film. The inter-floating-gate insulating layer includes a third insulating film and a fourth insulating film having a charge trap property which are stacked.

Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.

Abstract: A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.

Abstract: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming an shallow trench isolation (STI) in a substrate, sequentially forming an oxide layer and a nitride layer over the substrate, patterning the nitride layer and the oxide layer to expose a portion of the substrate adjacent to the STI layer, forming a field oxide layer contacting the STI layer in the exposed portion of the substrate, removing the nitride layer, etching a portion of the patterned oxide layer to form a first gate oxide layer contacting the field oxide layer, forming a second gate oxide layer over the substrate, and forming a gate pattern over the field oxide layer, the first gate oxide layer, and the second gate oxide layer.

Abstract: A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Abstract: A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

Abstract: A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.

Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract: A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.

Abstract: An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth.

Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Abstract: A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s).

Abstract: A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess.

Abstract: One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first contact trench. The semiconductor further includes a second contact trench extending into the semiconductor body at the second side. The second contact trench includes a second conductive material electrically coupled to the semiconductor body adjoining the second contact trench.