Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: A method of fabricating an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, depositing a high-density plasma (HDP) oxide layer partially filling the trench by supplying an HDP deposition source, etching an overhang generated while the HDP oxide layer is deposited using a fluorine-containing etching gas, depositing a liner HDP oxide layer on the HDP oxide layer by supplying an inert gas and an HDP deposition source such that fluorine (F) is trapped in the liner HDP oxide layer, performing an isotropic etching on an overhang portion of a side surface of the HDP oxide layer using the fluorine (F) trapped in the liner HDP oxide layer, and forming an HDP capping layer on the liner HDP oxide layer to fill a remaining portion of the trench.

Abstract: A plasma etching method for etching an object to be processed, which has at least an etching target layer and a patterned mask layer formed on the etching target layer, to form a recess corresponding to a pattern of the mask layer in the etching target layer, includes a first plasma process of forming deposits on the etching target layer at least around a boundary between the etching target layer and the mask layer in an opening portion constituting the pattern of the mask layer, and a second plasma process of forming the recess by etching the etching target layer after the first plasma process. An edge portion of an upper sidewall constituting the recess is rounded off in the second plasma process.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.

Abstract: A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area, forming a trench in the inactive area of the semiconductor substrate, forming a sacrifice oxide layer on an inner surface of the trench, forming a liner oxide layer on the sacrifice oxide layer, forming a gap-fill oxide layer as a device isolation layer on the liner oxide layer to fill up the trench, forming a buffer oxide layer on top surfaces of the liner and sacrifice oxide layers of the device isolation layer, and forming a gate oxide layer on the high voltage device area of the semiconductor substrate to have a uniform thickness.

Abstract: A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof.

Abstract: A method of forming an isolation layer in a semiconductor memory device is disclosed. After a trench is formed in a semiconductor substrate, a plasma nitrification annealing process is performed before and preferably after a wall oxide layer is formed to prevent trap charges and degradation problems at the interface and sidewalls of a tunnel insulating layer due to PSZ stress induced in a subsequent process. Accordingly, a variation in the ISPP step can be prevented.

Abstract: Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are formed in the periphery. Array isolation regions are disposed around at least a portion of at least some of the array devices and periphery isolation regions are disposed around at least a portion of at least some of the periphery devices. Within the semiconductor imager, the periphery isolation regions are configured differently from the array isolation regions. The semiconductor image sensor may be included in as part of an imaging system that includes a processor.

Abstract: A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.

Abstract: A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.

Abstract: A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure.

Abstract: The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the removal of substance containing carbon or oxygen may be performed after the oxide liner and the silicon nitride liner are formed on the bottom surface of the shallow trench. The present invention also discloses a process of treating bottom surface of the shallow trench. After the bottom surface of the shallow trench is treated, the bubble defects due to the use of the silicon nitride liner can be avoided.

Abstract: A method for manufacturing a semiconductor device, comprises: (a) forming a first semiconductor layer on a semiconductor substrate in a first region and forming a second semiconductor layer on the semiconductor substrate in a second region, a thickness of the first semiconductor layer being larger than a thickness of the second semiconductor layer; (b) forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; (c) forming a first cavity between the third semiconductor layer and the semiconductor substrate in the first region, and a second cavity between the third semiconductor layer and the semiconductor substrate in the second region by removing the first semiconductor layer and the second semiconductor layer, the first cavity and the second cavity having an internal height different each other; (d) forming an insulation layer inside the first cavity and the second cavity so that the first cavity remains a third cavity defined by the insulation layer formed both

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a pad oxide layer on a semiconductor substrate, forming a pad nitride layer on the pad oxide layer, forming a capping layer on the pad nitride layer, patterning the capping layer, the pad nitride layer, and the pad oxide layer by a photolithography method to expose portions of the semiconductor substrate, forming a field oxidation layer having bird's beaks, the bird's beaks being formed under the pad nitride layer, forming trenches in the semiconductor substrate by anisotropically etching the field oxide layer and the semiconductor substrate using the pad nitride layer as a mask, removing the capping layer, the pad nitride layer, the pad oxide layer, and the bird's beaks, and forming an isolation region in the trenches.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench inside a semiconductor substrate, forming a fluid insulating layer over the semiconductor substrate, thereby filling the trench with the fluid insulating layer, curing the semiconductor substrate by plasma oxidation to densify the fluid insulating layer, and planarizing the fluid insulating layer to form an isolation layer.

Abstract: Provided is a method of forming a trench in a semiconductor device capable of improving gap-fill performance. In one method of forming a trench in a semiconductor device, an oxide layer and a mask layer are sequentially formed on a substrate. The mask layer is selectively patterned to form a mask layer pattern. The oxide layer and the substrate are patterned using the mask layer pattern as a mask to form an oxide layer pattern and a trench having a predetermined depth from a surface of the substrate. A liner oxide layer is formed in the trench. A wet etching process is performed on the substrate to remove the liner oxide layer from the trench. A device isolation layer is formed in the trench from which the liner oxide layer has been removed. Then, the mask layer pattern and the oxide layer pattern are removed from the substrate.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.

Abstract: A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.

Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.

Abstract: This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjacent to the deposited deformable material such that at least a portion of the oxidized portion of the oxidizable layer interacts with the at least one portion of the deformable material to apply a localized pressure upon the at least one portion of the deformable material.

Abstract: A method for preventing wafer edge peeling in a metal wiring process. A buffer layer is formed between a diffusion barrier layer of a metal wiring substructure and a semiconductor substrate. The buffer layer is an insulating dielectric layer, preferably a silicon oxide layer, or a polysilicon layer. The silicon oxide layer is formed in a process for forming a Shallow Trench Isolation (STI) structure. Using the above processes, the structure of direct contact between the diffusion barrier layer of the metal wiring structure and the semiconductor substrate can be avoided, and hence wafer edge peeling can be avoided without any modification to a conventional semiconductor fabrication procedure and with low cost and improved operability. This method is applicable to various semiconductor fabrication processes.

Abstract: A method of manufacturing a semiconductor device comprises at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract: A method for forming a shallow trench isolation structure is described. A trench is formed in a substrate, and then a liner layer is formed in the trench. A portion of the liner layer around the top corner of the trench is removed, and then the trench is filled with an insulating material.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

Abstract: A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Abstract: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region; forming a groove portion in the element separation structure forming region; forming a groove portion oxide film in the groove portion; forming a pre-filling oxide film for filling the groove portion; removing the pre-filling oxide film; forming a resist layer on the silicon nitride film and the pre-filling oxide film; forming a resist mask on the element separation structure forming region; removing the silicon nitride film and the first thermal oxide film; forming a second thermal oxide film on the substrate; and removing the second thermal oxide film and leveling the pre-filling oxide film to form a filling portion.

Abstract: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the oxide film; exposing the upper surface of the semiconductor projection by polishing the insulating layer and the oxide film; forming a gate insulating layer at a lower region of the semiconductor projection; and etching the insulating layer and the oxide film on the substrate.

Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

Abstract: A method for forming an isolation structure of a semiconductor device including a substrate where a gate insulating layer, a gate conductive layer, and a pad nitride layer are already formed includes etching the pad nitride layer, the gate conductive layer, the gate insulating layer and a portion of the substrate to form a trench, forming a wall oxide layer along an inner surface of the trench, forming a first insulating layer over a first resulting structure, including the wall oxide layer, to partially fill the trench, forming a second insulating layer using a spin coating method over a second resulting structure, including the first insulating layer, to fill the trench, polishing the first and second insulating layers using the pad nitride layer as a polish stop layer, removing the pad nitride layer, recessing the first and second insulating layers, and recessing the second insulating layer to a predetermined depth.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier layer (15) to an upper part (O) of the inner walls of the trench (3), and production of a first oxide layer (7) on a lower part (U) of the inner walls, said lower part not being covered by the oxidation barrier layer (15), by means of thermal oxidation of the uncovered (U) part of the inner walls.

Abstract: In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined by a device isolation layer. The device isolation layer has a dual structure that includes a diffused isolation layer and a trench isolation layer. The diffused isolation layer is formed in the semiconductor substrate, and surrounds the base and the bottom sidewall of the device region, and the trench isolation layer surrounds the upper sidewall of the device region by vertically penetrating the epitaxial layer.

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench.

Abstract: A storage device having a read/write mechanism including a cantilever portion. The cantilever portion includes a non-single-crystal silicon body portion and a single crystal silicon tip.

Abstract: The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region.

Abstract: The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask over a substrate, etching a trench in the substrate through the hardmask, forming a liner in the trench, depositing an interfacial layer over the liner within the trench and over the hardmask and filling the trench with a dielectric material.

Abstract: The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a first atmosphere, which contains oxygen, and whose oxygen partial pressure is set in a range of 16 to 48 Torr, oxidizing the polymer film in a second atmosphere containing water vapor to form an oxide film containing a silicon oxide as a main component, after holding the work piece in the first atmosphere, and removing an upper portion of the oxide film to remain a lower portion of the oxide film in the trench.

Abstract: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

Abstract: A silicon oxide film (12) and a silicon nitride film (13) are sequentially formed over a silicon substrate (11) having a plane orientation (100). A trench (14) is formed with the patterned silicon nitride (13) as a mask. Argon is ion-implanted from the direction normal to a plane orientation (111) of the interior of the trench (14), followed by formation of an oxide film.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.