Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

Abstract: A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a control gate layer overlies the intergate dielectric layer. A first silicon oxide layer is formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extends across a first portion of an edge of the tunnel dielectric layer. A second silicon oxide layer is formed on a sidewall of the trench and extends across a second portion of the edge of the tunnel dielectric layer.

Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

Abstract: The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.

Abstract: A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

Abstract: Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.

Abstract: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing walls, of a second material, are formed within the opening which are laterally displaced inwardly of the opposing sidewalls, a space being received between the opposing walls and the opposing sidewalls, with monocrystalline material being exposed between the opposing walls within the opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. Other aspects and implementations are contemplated.

Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Abstract: A formation method and resulting strained semiconductor device are provided, the formation method including forming transistors on a substrate, each transistor having a gate disposed over a channel region, etching or annealing an elongated trench between adjacent channel regions, where the trench has a lower boundary that is deeper towards its ends than towards its center, and conformably embedding an elongated stress region in the trench between adjacent channel regions; and the resulting strained semiconductor device including transistors, each having a gate disposed over a channel region, and elongated stress regions disposed between adjacent channel regions, wherein each of the elongated stress regions has a lower boundary that is deeper towards its ends than towards its center.

Abstract: The invention relates to a method for forming microcavities (118) of different depths in a layer (102) based on at least an amorphous or monocrystalline material, comprising at least the following steps in which: at least one shaft and/or trench is formed in the layer (102) so as to extend through one face (101) thereof, such that two sections of the shaft and/or the trench, in two different planes parallel to the face (101), are aligned in relation to one another along an alignment axis forming a non-zero angle with a normal to the plane of said face (101); and the layer (102) is annealed in a hydrogenated atmosphere so as to transform the shaft and/or trench into at least two microcavities (118).

Abstract: A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.

Abstract: A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.

Abstract: A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

Abstract: A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate embodiment, nanoholes are patterned into a silicon nitride layer to expose an elemental silicon surface of a substrate. Group II-VI semiconductor material is grown in the holes until the layers fill the holes and coalesce to form a uniform layer of a desired thickness. Suitable materials for the substrate include silicon and silicon on insulator materials and cadmium telluride may be used as the Group II-VI semiconductor.

Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.

Abstract: A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer.

Abstract: Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

Abstract: A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.

Abstract: A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.

Abstract: A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the second pillar regions being provided in paired state and alternately, in a device portion and a terminal portion surrounding the device portion, along a surface on the side of a second electrode disposed on the opposite side of the first semiconductor region from the first electrode. The semiconductor device further includes a lateral RESURF (reduced surface field) region of the second conductivity type disposed at a surface portion, on the opposite side from the first semiconductor region, of the second semiconductor region in the terminal portion.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.

Abstract: An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is formed in the substrate adjacent to a sidewall of the trench.

Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

Abstract: An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract: A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick film region. The thin film region includes a first semiconductor layer deposited on the support substrate, and the thick film region includes the first semiconductor layer and a second semiconductor layer deposited on a part of the first semiconductor layer. The first STI-type isolation region is disposed at the thin film region. The second STI-type isolation region is disposed at the thick film region. The alignment mark region is disposed at the thick film region. An alignment mark to be used for alignment of the second STI-type isolation region is disposed at the alignment mark region.

Abstract: A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

Abstract: A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

Abstract: A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out lateral epitaxial overgrowth to form a bridged lateral overgrowth formation overlying the trench cavity. The bridged lateral overgrowth formation provides a substrate surface on which epitaxial layers can be grown in the fabrication of microelectronic devices such as laser diodes, high electron mobility transistors, ultraviolet light emitting diodes, and other devices in which low dislocation density is critical. The epitaxial substrate structures of the invention can be formed without the necessity for deep trenches, such as are required in conventional Pendeo epitaxial overgrowth structures.

Abstract: Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of the semiconductor substrate layer. A semiconductor layer is then formed in the openings directly upon the exposed portions of the semiconductor substrate layer using a second material different from the first material (e.g., silicon germanium or silicon). In other examples, multiple semiconductor layers may be formed using alternating materials.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.