Abstract: The present invention provides a method for forming a field oxide film on a semiconductor device. In particular, the present invention provides a method for forming a field oxide film on a semiconductor device using a silicon epitaxial layer to improve a Shallow Trench Isolation (STI) process.

Abstract: A transistor structure has a recess formed in the upper surface of its base layer, an epitaxial (epi) layer grown on the upper surface in a manner to create a surface depression in the outer surface of the epi layer, the surface depression being generally aligned with the recess. A semiconductor element, such as a well or a gate, is formed on the epi layer aligned with the recess.

Abstract: A new method of fabricating shallow trench isolations has been achieved. No final polishing down process is needed. A silicon substrate is provided. A pad oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer, the pad oxide layer, and the silicon substrate are patterned to form trenches for planned shallow trench isolations. A liner oxide layer is grown overlying the semiconductor substrate is the trenches. A silicon dioxide spacer layer is deposited overlying the silicon nitride layer and the liner oxide layer to partially fill the trenches. The silicon dioxide spacer layer and the liner oxide layer are anisotropically etched to form sidewall spacers inside the trenches and to expose the bottom of said trenches. A silicon layer is selectively grown overlying the semiconductor substrate in the trenches. The silicon layer partially fills the trenches. A trench oxide layer is formed overlying the silicon layer.

Abstract: There is disclosed a triple well of a semiconductor device using SEG and method of forming the same.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A method of manufacturing semiconductor components includes etching two trenches (105, 106, 805, 806, 1205, 1206) into a surface of a substrate (101, 801, 1201), lining the two trenches (105, 106, 805, 806, 1205, 1206) with an electrically insulative layer (107, 807, 1207) that is never completely removed from a first one of the two trenches (105, 106, 805, 806, 1205, 1206), and simultaneously filling the two trenches (105, 106, 805, 806, 1205, 1206) with a material wherein the material is never completely removed from the first one of the two trenches (105, 106, 805, 806, 1205, 1206) and wherein the second one of the two trenches (105, 106, 805, 806, 1205, 1206) becomes electrically coupled to the substrate (101, 801, 1201).

Abstract: A semiconductor light-receiving device including (a) a semiconductor substrate, (b) a multi-layered including a first buffer layer having a first electrical conductivity and lying on the semiconductor substrate, a first clad layer having a first electrical conductivity and lying on the first buffer layer, a light-absorbing layer having a first electrical conductivity and lying on the first clad layer, a second clad layer having a second electrical conductivity and lying on the light-absorbing layer, and a second buffer layer having a second electrical conductivity and lying on the second clad layer, (c) a first electrode formed on the second buffer layer, and (d) a second electrode formed on a lower surface of the semiconductor substrate. The multi-layered structure has at least one portion which is inclined to a direction in which a light introduced into the device is directed. For instance, the multi-layered structure has opposite end portions inclined to the direction.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown in top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls.

Abstract: A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled with polysilicon; a gate conductor formed over the trench region; and source/drain regions formed within the well region laterally aligned to the gate conductor. A suitable method to form the MOS transistor includes the acts of: forming a well region in a semiconductor substrate; forming a trench region in the well region; forming an isolator in a corner of the trench region; filling the trench region with polysilicon; forming a gate conductor formed over the trench region; and forming source/drain regions within the well region on opposite sides of the gate conductor.

Abstract: A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer.

Abstract: A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.

Abstract: A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench.

Abstract: A method of forming shallow trench isolations is achieved. STI structures so formed do not exhibit isolation oxide thinning due to dishing and erosion problems during the oxide CMP process. A silicon substrate is provided. A first dielectric layer is formed overlying the silicon substrate. A silicon nitride layer is deposited. The silicon nitride layer, the first dielectric layer, and the silicon substrate are etched to form trenches for planned shallow trench isolations. A second dielectric layer is deposited overlying the silicon nitride layer and the trenches. The second dielectric layer is etched to form sidewall spacers inside the trenches. A silicon layer is selectively grown overlying the silicon substrate only where the silicon substrate is exposed in the trenches, and wherein the step of growing is stopped before the silicon layer exceeds the top surface of the silicon nitride layer.

Abstract: The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad layer. Next, a second stacked layer is formed over the first stacked layer. An opening is defined in the second stacked layer, the first stacked layer, and the pad layer. The opening extends down to the substrate. A portion of the substrate is then removed for forming an upper-half portion of a trench by using the second stacked layer as a mask. A sidewall structure is formed on the opening. Next, a portion of the substrate is removed for forming a lower-half portion of the trench by using the sidewall structure as a mask. The sidewall structure and the second stacked layer are removed. Following with the formation of a first insulating layer over the trench, a second insulating layer is formed over the first insulating layer and over the first stacked layer.

Abstract: According to a method of fabricating a selective epitaxial film, a thin insulating film serving as a mask is formed on the entire surface of a semiconductor substrate having a (100) plane. An opening portion reaching the semiconductor substrate is formed in a desired region of the thin insulating film. An epitaxial film is selectively grown in the opening portion. The semiconductor substrate having the selective epitaxial film formed thereon is annealed at at least a pressure of 1,000 Pa and at least a temperature of 800.degree. C. to fill a gap on the contact surface between the thin insulating film and the selective epitaxial film.

Abstract: The first trench is formed in the region of the semiconductor substrate, in which an element isolation region is to be formed, and the first buried member, which is insulative, is buried in the first trench. Then, the second trench, having a width smaller than that of the first trench, is made in the first buried member, and the portion of the semiconductor substrate which is located at the bottom portion of the first trench, and the insulating second buried member is buried in the second trench, thereby forming the element isolation region.

Abstract: A manufacturing method of a semiconductor integrated circuit utilizing a trench isolated region to control the occurrence of parasitic transistors without narrowing the element region by forming first and second openings 4A, 4B on a silicon substrate for the purpose of element isolation, forming an amorphous silicon film thereon, then leaving the amorphous silicon film behind only a surface of a side wall of the opening by performing anisotropy etching. After oxidizing the surface of the amorphous silicon film and inside base, the opening is filled with a silicon oxide film.

Abstract: A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.

Abstract: An isolation layer structure of a semiconductor device includes a substrate; a first insulating layer having a predetermined width and thickness which is formed in a predetermined portion of the substrate; and a second insulating layer which is formed in a predetermined portion of the substrate and which surrounds the first insulating layer.