Abstract: Disclosed is an apparatus and method for yield enhancement of making a semiconductor device. The apparatus for yield enhancement of making a semiconductor device comprises: a semiconductor device comprising an epitaxial layer in which a defect is included, and a photo-resistor on the epitaxial layer and covering the defect; an image recognition system to detect and identify a location of the defect; and an exposing module comprising a first light source to expose a part of the photo-resistor substantially corresponding to the detected defect identified by the image recognition system.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: A manufacturing method suitable for solar modules is provided. A solar cell string 25 is inspected for the presence of any defective solar cell 20. When a defective solar cell 20a is found, the wiring members 30a, 30b bonding the defective solar cell 20a to the solar cells 20b, 20c adjacent to the defective solar cell 20a are disconnected, and the defective solar cell 20a is removed from the solar cell string 25. The wiring member pieces 33a, 33b are connected electrically to a new solar cell 20d, and the tip portions of the wiring member pieces 33a, 33b are connected electrically to the disconnected pieces 30a1, 30b1 connected electrically to the adjacent solar cells 20b, 20c. The wiring member pieces 33a, 33b are connected electrically while interposed between the disconnected pieces 30a1, 30b1 and the adjacent solar cells 20b, 20c.

Abstract: Disclosed is a method for manufacturing an organic EL display, which comprises: a step of preparing an organic EL panel that comprises a substrate and organic EL elements arranged as a matrix on the substrate, wherein each organic EL element has a pixel electrode arranged on the substrate, an organic layer arranged on the pixel electrode, a transparent counter electrode arranged on the organic layer, a protective layer arranged on the transparent counter electrode, and a color filter arranged on the protective layer, and a defect portion present in the organic layer in each organic EL element is detected; a step of destroying a region of the transparent counter electrode positioned above the defect portion by irradiating the region with laser light through the color filter; and a step wherein a region of the color filter positioned above the defect portion is removed.

Abstract: The present invention provides a method for repairing open line defect on LCD array substrate, which includes: when discovering open line defect on a pattern on LCD array substrate, identifying a repair line path of the open line on the pattern and scanning the repair line path; based on the result of scanning the repair line path, dividing the repair line path into at least two path segments and disposing corresponding coating speed for each path segment; and for each path segment, performing coating at the corresponding speed to form connected coating on the repair line path. The present invention also provides a device for repairing open line defect on LCD array substrate. As such, the present embodiment can increase success rate for repairing open lines.

Abstract: A digital X-ray detector includes a scintillator that is configured to absorb radiation emitted from an X-ray radiation source and to emit light photons in response to the absorbed radiation. The detector also includes a complementary metal-oxide-semiconductor (CMOS) light imager that is configured to absorb the light photons emitted by the scintillator. The CMOS light imager includes a first surface and a second surface. The first surface is disposed opposite the second surface. The scintillator contacts the first surface of the CMOS light imager. The CMOS light imager further includes a repaired CMOS pixel array with at least one defective CMOS pixel isolated from a common column data line, a row select scan line, or a rest line within the CMOS pixel array.

Abstract: The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element that replaces a defective element is mounted on the same wiring pattern on which the defective element is mounted. The defective element or a trace that remains after removal of the defective element is sealed by a same sealing member by which the new light-emitting element is sealed.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract: A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.

Abstract: A method of fabricating an organic electroluminescent device (OELD) according to the present invention has steps of repairing a pixel region by irradiating a laser on a drain contact hole of a passivation layer in a pixel region in need of the repair; and disabling the connection between an organic electroluminescent diode and a drain electrode of a driving thin film transistor (TFT), where the pixel region of the OELD has i) the driving TFT comprising the drain electrode, ii) the passivation layer covering the driving TFT, while comprising the drain contact hole exposing the drain electrode of the driving TFT, and iii) the organic electroluminescent diode connected to the drain electrode of the driving TFT via the drain contact hole.

Abstract: Methods for repairing a carbon depleted low-k material in a low-k dielectric film layer of a semiconductor wafer include providing a proximity head with a plurality of nozzles disposed on a surface of the proximity head. A repair chemistry having a hydrocarbon group is applied to a portion of the semiconductor wafer that includes carbon depleted low-k material, through the proximity head. The application is used to deliver carbon from the repair chemistry into the carbon depleted low-k material so as to cause replacement of a hydrogen ion within a hydroxyl group in the carbon depleted low-k material with carbon containing hydrocarbon group of the repair chemistry. The carbon containing hydrocarbon group forms a bond with suspended oxygen ion of the hydroxyl group thereby substantially repairing the low-k dielectric layer. The semiconductor wafer is then moved to expose other portions of the semiconductor wafer to the repair chemistry.

Abstract: A repairing method, repairing device and repairing structure for repairing a signal line of an array substrate having the disconnected defect , including: setting a repairing route according to a position of the disconnected defect and determining a position at which a filling portion is required to be formed according to the repairing route; forming the filling portion at the position at which the filling portion is required to be formed; and forming a repairing line along the repairing route. By detecting the repairing route before repairing the disconnected defect by forming the filling portion according to the repairing route, the present disclosure can avoid the disconnection of the repairing line caused by great height differences of the surface under the repairing line and improve the repairing success rate of the disconnected defect.

Abstract: The present disclosure provides a repairing method, a repairing structure and a repairing system for a disconnected defect, the repairing method includes: forming a first repairing line connecting two ends of a disconnected portion of a scanning line; forming an insulation layer covering the first repairing line; and forming a second repairing line connecting two ends of a disconnected portion of a data line with the insulation layer located at an intersection of the first repairing line and the second repairing line. By forming the insulation layer between the first repairing line and the second repairing line, the present disclosure avoids the short circuit generated after the scanning line and the data line are repaired, repairs the disconnected defect at the intersection of two metal layers, improves the yield rate of the repairing of the disconnected defect, and reduces manufacturing cost.

Abstract: A defect detection method for an organic EL element having a first electrode, a second electrode, and a functional layer and a light-emission layer disposed between the electrodes, including: applying a first voltage, between the electrodes, that, when the organic EL element includes, between the electrodes, a defective portion that is a potential cause of non-light emission of the light-emission layer, reduces electrical resistance of a first portion, of the functional layer, corresponding to the defective portion and makes the organic EL element detectable as a dark spot, whose light-emission layer does not emit light; and after applying the first voltage, applying a second voltage between the electrodes and detecting whether or not the organic EL element is the dark spot, the second voltage, when the organic EL element does not include the defective portion, causing the light-emission layer to emit light.

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract: Discrete and diffuse defects in a surface are detected. Discrete defects that may compromise the performance may be repaired.

Abstract: The present invention provides a method for repairing open line defect on LCD array substrate, which includes: when discovering open line defect on a pattern on LCD array substrate, identifying a repair line path of the open line on the pattern and scanning the repair line path; based on the result of scanning the repair line path, dividing the repair line path into at least two path segments and disposing corresponding coating speed for each path segment; and for each path segment, performing coating at the corresponding speed to form connected coating on the repair line path. The present invention also provides a device for repairing open line defect on LCD array substrate. As such, the present embodiment can increase success rate for repairing open lines.

Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.

Abstract: An organic light emitting display apparatus and a method of inspecting the same, the organic light emitting display apparatus including a plurality of sub-pixels; a plurality of conductive line portions connected to the sub-pixels, the plurality of conductive line portions including at least two conductive lines connected in parallel to one another; and inspection thin film transistors (TFTs) disposed adjacent to one end and both ends of at least one conductive line of the conductive lines connected in parallel to one another.

Abstract: A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, molding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.

Abstract: A thin film transistor substrate includes a substrate including a display area including pixels and a periphery area where a driver for driving the pixels is disposed; first signal lines connected with the pixels and extended to the periphery area, and including a first short-circuit portion provided in the periphery area; second signal lines connected with the pixels and extended to the periphery area by crossing the first signal lines in an insulated manner; first connection members overlapping lateral ends of the first signal lines, disposed in lateral sides with respect to the first short-circuited portion and formed of a doped semiconductor; and first repairing conductors overlapping the lateral ends of the first signal line, disposed in the lateral sides with respect to the first short-circuited portion. Lateral ends of the first connection member are connected with the lateral ends of the first signal line through contact holes.

Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.

Abstract: A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler.

Abstract: A liquid crystal display device includes an array substrate and a color filter substrate, a plurality of gate lines and a plurality of data lines formed on the array substrate such that the gate lines and the data lines intersect each other to define a plurality of pixel regions, a plurality of thin film transistors formed at respective intersections of the gate lines and the data lines, a liquid crystal layer interposed between the array and color filter substrates, and a plurality of repair patterns formed on the first substrate. Each of the plurality of the repair patterns crosses a corresponding one of the data lines, and is along and adjacent to a corresponding one of the gate lines, such that the repair pattern includes protruding ends that protrude from the corresponding data line to repair a defect on the pixel regions.

Abstract: A thin film transistor substrate includes a capacitor including a first capacitor electrode and a second capacitor electrode on a substrate, a first wire connected to the first capacitor electrode, a second wire connected to the second capacitor electrode, a first conductive pattern layer spaced apart from the first capacitor electrode and the second capacitor electrode, a second conductive pattern layer spaced apart from the first conductive pattern layer and formed to overlap with the first conductive pattern layer, a first conductive wire pattern connected to the first conductive pattern layer, spaced apart from the second conductive pattern layer, and overlapping with the second wire in at least one area, and a second conductive wire pattern connected to the second conductive pattern layer, spaced apart from the first conductive pattern layer and the first conductive wire pattern, and overlapping with the first wire in at least one area.

Abstract: A thermoelectric conversion module includes a pair of heat transfer plates, p-type semiconductor blocks and n-type semiconductor blocks arranged between the heat transfer plates, and terminal electrodes formed respectively on inner surfaces of the heat transfer plates and connecting the semiconductor blocks in series. The heat transfer plates include holes reaching from an outer surface to the terminal electrodes, and grooves each formed between the terminal electrodes and communicating between the adjacent holes. If a disconnection occurs, for example, a pin of a tester is brought into contact with the terminal electrode via the hole to specify a disconnected portion, and the terminal electrodes are electrically connected by injecting conductive paste into the holes in the disconnected portion as well as the groove.

Abstract: Methods for improving the performance and lifetime of irradiated photovoltaic cells are disclosed, whereby Group-V elements, and preferably nitrogen, are used to dope semiconductor GaAs-based subcell alloys.

Abstract: Embodiments of the present invention relate to a reclaimed wafer, a method for reclaiming a wafer, a method for reclaiming a batch of wafers, and a method for forming electronic structures. After being reclaimed, the reclaimed wafers are essentially free of a residue.

Abstract: A method for etching trenches in an etch layer disposed below a patterned organic mask is provided. The patterned organic mask is treated, comprising flowing a treatment gas comprising H2 and N2, forming a plasma from the treatment gas, making patterned organic mask more resistant to wiggling, and stopping the flow of the treatment gas. Trenches are etched in the etch layer through the patterned organic mask.

Abstract: A method for repairing a solar cell module includes the following steps. A solar cell module, which is provided, includes a first and a second solar cell serially connected. A first terminal is electrically connected to a first electrode layer of the first solar cell. A second terminal is electrically connected to a second electrode layer of the second solar cell. A polarity of the first electrode layer is the same as that of the second electrode layer. A biased voltage signal is generated and transmitted to the first solar cell and the second solar cell through the first terminal and the second terminal. The biased voltage signal includes a forward biased voltage part greater than zero and a reversed biased voltage part smaller than zero. The voltage value of the reversed biased voltage part is increasingly decreased in a step-like manner as time goes by.

Abstract: A method for manufacturing a thin film photoelectric conversion module includes the steps of forming a plurality of photoelectric conversion elements connected in series on a substrate, and carrying out reverse bias processing simultaneously on a group of photoelectric conversion elements including a plurality of the photoelectric conversion elements positioned with one or a plurality of the photoelectric conversion elements interposed between each of them, by applying a plurality of voltages electrically isolated from one another to the group of photoelectric conversion elements.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: An electronic package implemented in an electronic device may include a damaged connection that restricts electrical communication between components in the electronic package. For example, the damaged connection may restrict communication between a silicon unit, such as a processor die for example, and a printed circuit board. The damaged connection may be repaired without damaging other components in the electronic package by using a repair apparatus that includes a heating element and a cooling element. The heating element may be activated to transfer heat to the electronic package for reforming the damaged connection between components to enable effective electrical communication. The cooling element may be activated for cooling components in the electronic package to prevent damage due to the transfer of the heat from the heating element. The heating element and/or the cooling element may be activated in a predetermined pattern to facilitate the repair of the damaged connection.

Abstract: A semiconductor apparatus includes: a through-silicon via (TSV) formed in a silicon substrate; a first insulating layer formed to surround side and bottom portions of the TSV such that the TSV is isolated from the silicon substrate; a first conductive layer interposed between the first insulating layer and the silicon substrate and formed outside the TSV to surround the TSV.

Abstract: Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.

Abstract: A display device capable of suppressing decrease in capacitance and capable of reducing area even when a capacitor unit is repaired is provided. A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in an SD electrode layer and a second capacitor electrode provided in a GM electrode layer; a backup capacitor electrode provided in the TM electrode layer; a disconnect-able portion at which a connection between the first capacitor electrode and the power line can be disconnected; and a connectable portion at which the backup capacitor electrode and the power line can be connected, and the disconnect-able portion and the connectable portion overlap in a stacking direction.

Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.

Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: The present invention provides a radiation detection element that allows repairing of a defect portion, and that minimizes the number of pixels from which charges cannot be read out when repaired. Namely, in two adjacent pixels that are connected to a signal line having a defect portion where a defect has occurred and that are adjacent to the defect portion, the signal lines and the parallel lines are short-circuited to configure a parallel circuit parallel to the defect portion.

Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

Abstract: The present invention provides a LCD panel and a method for repairing the LCD panel. The LCD panel includes a plurality of data lines and a plurality of subpixel areas. Each subpixel area includes a corresponding pixel electrode and thin film transistor. The subpixel area including a spot defect is electrically connected to a neighboring subpixel area having the same color and in normal operation. The connection between the thin film transistor in the subpixel area including the spot defect and the corresponding data line and the connection between the thin film transistor and the corresponding pixel electrode are cut. Consequently, the subpixel area including the bright spot defect is repaired and able to display normally. The display quality of the LCD panel display is improved. Moreover, the present invention repair method is suitable for the repairing of LCD panels without storage capacitors.

Abstract: A method of repairing a defective pixel in a display apparatus includes cutting both sides of a region of the corresponding second signal wire of the defective pixel, forming an insulating layer to cover the second signal wires, forming contact holes adjacent to both sides of the cut region, respectively, such that an upper surface of the second signal wire is exposed, forming a repair metal layer on the insulating layer to contact the contact holes and the second signal wire, and forming a repair insulating layer to cover the repair metal layer.

Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.

Abstract: A manufacturing method of a liquid crystal panel, includes: cleaning a thin film transistor array substrate of the liquid crystal panel; performing an array detection on the cleaned thin film transistor array substrate; and processing the thin film transistor array substrate according to detecting result of the array detection. In the present disclosure, the TFT array substrate is cleaned after the array manufacturing process and is detected to determine whether the lines thereon are disconnected, and the disconnected lines are further repaired, which prevents the TFT array substrate with the disconnected lines from entering the cell device and reduces the scrap rate of the liquid crystal panel. Meanwhile, since the TFT array substrate is at first cleaned by the cleaning mechanism to remove the particles thereon and further is detected by the array detector, thus, the particles on the TFT array substrate is prevented from damaging the array detector.

Abstract: A method of manufacturing an organic EL device includes: irradiating a light-emitting region of the organic EL device which includes a defective portion with a laser beam under a first irradiation condition; observing a state of an irradiation mark formed in the light-emitting region through the irradiation with the laser beam in the irradiating under a first irradiation condition; determining a second irradiation condition for resolving a defect caused by the defective portion, based on the first irradiation condition and the observed state of the irradiation mark; and irradiating the light-emitting region with a laser beam under the second irradiation condition determined in the determining of a second irradiation condition.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.