Repair Or Restoration Patents (Class 438/4)
  • Publication number: 20130337583
    Abstract: A method for repairing process-related damage of a dielectric film includes: (i) adsorbing a first gas containing silicon on a surface of the damaged dielectric film without depositing a film in the absence of reactive species, (ii) adsorbing a second gas containing silicon on a surface of the dielectric film, followed by applying reactive species to the surface of the dielectric film, to form a monolayer film thereon, and (iii) repeating step (ii). The duration of exposing the surface to the first gas in step (i) is longer than the duration of exposing the surface to the second gas in step (ii).
    Type: Application
    Filed: May 23, 2013
    Publication date: December 19, 2013
    Applicant: ASM IP Holding B.V.
    Inventors: Akiko Kobayashi, Yosuke Kimura, Dai Ishikawa, Kiyohiro Matsushita
  • Publication number: 20130328020
    Abstract: A method of repairing a defective pixel in a display apparatus that includes forming an insulating layer to cover the plurality of second signal wires, cutting both sides of a region of the corresponding second signal wire of the defective pixel and the insulating layer to form both sides of a cut region, forming contact holes adjacent to the both sides of the cut region, respectively, such that an upper portion of the corresponding second signal wire is exposed, forming a repair metal layer on the insulating layer to contact the contact holes and the second signal wire, and forming a repair insulating layer to cover the repair metal layer.
    Type: Application
    Filed: October 31, 2012
    Publication date: December 12, 2013
    Inventors: Yul-Kyu LEE, Sun PARK, Kyu-Sik CHO
  • Publication number: 20130329508
    Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Stanton Petree Ashburn, Daniel L. Corum, Abha Singh Kasper, Harold C. Waite, Eric D. Rullan, Donald L. Plumton, Douglas A. Prinslow
  • Publication number: 20130329158
    Abstract: A slit-shaped repair hole (27S) for repairing a short circuit defect of adjacent pixel electrodes (27) is provided straddling a storage capacitance wiring line (22CsL) at at least one intersection of the edges of the plurality of the pixel electrodes (27) and the storage capacitance wiring line (22CsL).
    Type: Application
    Filed: February 16, 2012
    Publication date: December 12, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Teruki Kanamori
  • Publication number: 20130320323
    Abstract: A method for fabricating an organic electroluminescence device according to the present invention includes: preparing an organic electroluminescence device having a lower electrode, an organic layer including an emitting layer, an upper electrode, and a shorted part in which the lower electrode and the upper electrode are shorted; and irradiating a part surrounding the shorted part in which the lower electrode and the upper electrode are shorted to alter a material composing the lower electrode or the upper electrode and to form a space between the lower electrode and the upper electrode in a region corresponding to a region surrounded by an altered part.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 5, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yasuo Segawa, Tomomi Hiraoka
  • Patent number: 8592262
    Abstract: A method is used to prevent unwanted electrical contacts between various electrically conducting surfaces and lines in a display panel due to an n+ a-Si residue and/or ITO debris. The method provides a clearing pattern including at least a cleared area in the passivation layer for preventing the residue or debris from locating at the cleared area. As such, if an n+ a-Si residue happens to be deposited under the passivation layer, the part of the residue located in the cleared area is removed by an a-Si selective etching process, for example. Furthermore, with the cleared area, ITO debris deposited on the section of the dielectric layer deposited on the signal line can be electrically isolated from the electrode.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: November 26, 2013
    Assignee: AU Optronics Corporation
    Inventor: Han-Chung Lai
  • Publication number: 20130307151
    Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Junjing Bao, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20130302915
    Abstract: A thin film transistor array panel includes: a substrate; a gate line and a storage electrode that are disposed on the substrate; a data line that crosses the gate line and storage electrode line; a thin film transistor that is connected with the gate line and data line; and a pixel electrode that is connected to the thin film transistor. The storage electrode includes a first storage electrode that is parallel to the gate line, second storage electrodes that extend on opposing sides of the data line from the first storage electrode, a connection part that crosses the data line and connects pairs of the second storage electrodes, and a connection bridge that crosses the gate line and connects a second storage electrode to a second storage electrode of an adjacent pixel.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Applicant: Samsung display Co., Ltd.
    Inventors: Jong-Hyuk Lee, Bon-Yong Koo, Sun-Mi Kim, Ju Hyeon Baek, Ji Young Jeong
  • Publication number: 20130299946
    Abstract: A method that includes, in the sequence set forth, (1) temporarily fixing a substrate onto a support via a temporary fixing material including a central section (A) having two or more layers and a peripheral section (B) with solvent resistance, section (B) being in contact with a peripheral portion of the support on the substrate side and with a peripheral portion of the substrate on the support side, section (A) being in contact with a central portion of the support on the substrate side and with a central portion of the substrate on the support side, the temporary fixing thus resulting in a stack in which section (A) is covered with the support, section (B) and the substrate; (2) processing the substrate and/or transporting the stack; (3) dissolving section (B) with a solvent; and (4) heating the residue of the temporary fixing material and separating the substrate from the support.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 14, 2013
    Inventor: JSR CORPORATION
  • Publication number: 20130295695
    Abstract: The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.
    Type: Application
    Filed: April 10, 2013
    Publication date: November 7, 2013
    Inventors: Gildardo Delgado, Gary Janik
  • Publication number: 20130295696
    Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
  • Patent number: 8574929
    Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 5, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist
  • Publication number: 20130288399
    Abstract: An energy beam processing apparatus cutting an interconnection by irradiating the interconnection with an energy beam while scanning, the energy beam processing apparatus including an irradiation unit which irradiates the interconnection with the energy beam while scanning; a measurement unit which measures a resistance value of the interconnection; and a control unit which controls a scan and an irradiation of the energy beam by the irradiation unit, the control unit controlling at least one of a scan rate and an irradiation intensity of the energy beam in accordance with a resistance value measured by the measurement unit, and controlling the irradiation unit to stop the irradiation of the energy beam when the resistance value measured by the measurement unit exceeds a prescribed value.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki FUJIMOTO
  • Publication number: 20130286758
    Abstract: A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventor: Byung-Chul KIM
  • Publication number: 20130280822
    Abstract: Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected.
    Type: Application
    Filed: June 20, 2013
    Publication date: October 24, 2013
    Inventors: Kuo-Chang Su, Chun-Hsin Liu, Min-Feng Chiang
  • Publication number: 20130277758
    Abstract: A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over the active area. Spaces between the dummy gates are filled with a dielectric gap fill material such that one or more keyholes are formed in the dielectric gap fill material between the dummy gates. The dummy gates are removed to reveal a plurality of gate canyons in the dielectric gap fill material. A mask is formed that divides at least one of the gate canyons, blocks off one or more of the keyholes and leaves one or more of the keyholes un-blocked. At least one gate stack material is deposited onto the wafer filling the gate canyons and the un-blocked keyholes. A FET device is also provided.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 8563993
    Abstract: A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in a GM electrode layer and a second capacitor electrode connected to a line and provided in an SD electrode layer; a backup capacitor element having a first backup capacitor electrode provided in the GM electrode layer and a second backup capacitor electrode connected to the power line and provided in the SD electrode layer; a disconnect-able portion at which a connection between the second capacitor electrode and the line can be disconnected; and a connectable portion at which the first backup capacitor electrode and the line can be connected, and the disconnect-able portion and the connectable portion are arranged at a position in which the disconnect-able portion and the connectable portion overlap in a stacking direction.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Shirouzu, Kenichi Tajika
  • Patent number: 8563332
    Abstract: Provided is a wafer reclamation method for reclaiming a semiconductor wafer, on which a different material layer is formed, by removing the different material layer. The wafer reclamation method includes a physically removing step of physically removing the different material layer, a film forming step of forming a film on a surface of the semiconductor wafer from which the different material layer has been removed in the physically removing step, and a dry etching step of etching the semiconductor wafer by plasma together with the film formed in the film forming step.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Shogo Okita, Gaku Sugahara, Hiroyuki Suzuki, Ryuzou Houchin, Mitsuru Hiroshima
  • Patent number: 8563331
    Abstract: A process for forming an electronic device can include fabricating an electronic device having a first workpiece including a first electronic component that includes a first organic layer. The process can also include repairing the electronic device after fabrication to provide electrical connections for initial non-functional electrical elements.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: October 22, 2013
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Jian Wang, Gang Yu
  • Publication number: 20130256638
    Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.
    Type: Application
    Filed: March 19, 2013
    Publication date: October 3, 2013
    Applicant: Sony Corporation
    Inventors: Masanao Uesugi, Jiro Yamada, Mitsuo Morooka, Yasunobu Hiromasu
  • Publication number: 20130256723
    Abstract: An organic light emitting diode (OLED) display includes a light-emitting region including an organic emission layer and a non-light-emitting region neighboring the light-emitting region. The OLED display includes a first electrode positioned at the light-emitting region and including a plurality of division regions divided according to a virtual cutting line crossing the light-emitting region, an organic emission layer positioned on the first electrode, a second electrode positioned on the organic emission layer, a driving thin film transistor connected to the first electrode, and a plurality of input terminals positioned at the non-light-emitting region and respectively connecting between each of division regions and the driving thin film transistor.
    Type: Application
    Filed: September 12, 2012
    Publication date: October 3, 2013
    Inventors: Guang hai JIN, Jae-Beom CHOI, Kwan-Wook JUNG, June-Woo LEE, Moo-Jin KIM, Na-Young KIM
  • Publication number: 20130252349
    Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay Anil Pradhan, Stanislav S. Todorov, Kurt Decker-Lucke, Klaus Petry, Benjamin Colombeau, Baonian Guo
  • Publication number: 20130248844
    Abstract: A method for manufacturing an organic electroluminescence device includes: preparing an organic electroluminescence device including a lower electrode, an organic layer including a light-emitting layer, and an upper electrode and having a part in which the lower electrode and the upper electrode are shorted, at least one of the lower electrode and the upper electrode being made of a transparent conductive material; and irradiating the transparent conductive material in at least one of the part where the lower electrode and the upper electrode are shorted and a part around the shorted part with a femtosecond laser, and increasing resistance by changing a structure of the transparent conductive material.
    Type: Application
    Filed: December 1, 2010
    Publication date: September 26, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Tomomi Hiraoka
  • Patent number: 8535767
    Abstract: A method for repairing process-related damage of a dielectric film formed on a substrate caused by processing the dielectric film includes: irradiating the damaged dielectric film with UV light in an atmosphere of hydrocarbon-containing gas to restore the surface of the dielectric film; and irradiating the surface-restored dielectric film with UV light in an atmosphere of oxygen gas to partially remove the hydrocarbon film.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 17, 2013
    Assignee: ASM IP Holding B.V.
    Inventor: Yosuke Kimura
  • Publication number: 20130235292
    Abstract: A liquid crystal display panel includes: a plurality of switching elements each provided on a transparent substrate (10) for each sub-pixel and having a drain electrode (14b); an interlayer insulating film (17) provided to cover the switching elements and including an inorganic insulating film (15) and an organic insulating film (16) sequentially layered; a capacitor electrode (18a) provided on the interlayer insulating film (17); a capacitor insulating film (19) provided to cover the capacitor electrode (18a); a plurality of pixel electrodes (20a) which are provided on the capacitor insulating film (19) and face the capacitor electrode (18a); and a connection region (R) at which the drain electrode (14b) and the capacitor electrode (18a) overlap each other via the inorganic insulating film (15) exposed from the organic insulating film (16).
    Type: Application
    Filed: January 24, 2012
    Publication date: September 12, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Yukinobu Nakata
  • Patent number: 8530246
    Abstract: A method for controlling the threshold voltage of a semiconductor element having at least a semiconductor as a component is characterized in including a process to measure one of a threshold voltage and a characteristic value serving as an index for the threshold voltage; a process to determine one of the irradiation intensity, irradiation time, and wavelength of the light for irradiating the semiconductor based on one of the measured threshold voltage and the measured characteristic value serving as the index for the threshold voltage; and a process to irradiate light whose one of the irradiation intensity, irradiation time, and wavelength has been determined onto the semiconductor; wherein the light irradiating the semiconductor is a light having a longer wavelength than the wavelength of the absorption edge of the semiconductor, and the threshold voltage is changed by the irradiation of the light.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 10, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Ofuji, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko, Ryo Hayashi
  • Publication number: 20130230932
    Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Inventors: Venkatraghavan Bringivijayaraghavan, Jason M. Brown
  • Patent number: 8524512
    Abstract: Method for repairing copper diffusion barrier layers on a semiconductor solid substrate and repair kit for implementing this method. One subject of the present invention is a method for repairing a surface of a substrate coated with a discontinuous copper diffusion barrier layer of a titanium-based material. According to the invention, this method comprises: a) the contacting of the surface with a suspension containing copper or copper alloy nanoparticles for a time of between 1 s and 15 min; and b) the contacting of the thus treated surface with a liquid solution having a pH of between 8.5 and 12 and containing: at least one metal salt, at least one reducing agent, at least one stabilizer at a temperature of between 50° C. and 90° C., preferably between 60° C. and 80° C., for a time of between 30 s and 10 min, preferably between 1 min and 5 min, in order to thus form a metallic film having a thickness of at least 50 nanometers re-establishing the continuity of the copper diffusion barrier layer.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: September 3, 2013
    Assignee: Alchimer
    Inventor: Vincent Mevellec
  • Publication number: 20130224889
    Abstract: A charged particle beam apparatus is provided that enables faster semiconductor film deposition than the conventional deposition that uses silicon hydrides and halides as source gases. The charged particle beam apparatus includes a charged particle source 1, a condenser lens electrode 2, a blanking electrode 3, a scanning electrode 4, a sample stage 10 on which a sample 9 is mounted, a secondary charged particle detector 8 that detects a secondary charged particle 7 generated from the sample 9 in response to the charged particle beam irradiation, a reservoir 14 that accommodates cyclopentasilane as a source gas, and a gas gun 11 that supplies the source gas to the sample 9.
    Type: Application
    Filed: September 22, 2011
    Publication date: August 29, 2013
    Applicants: HITACHI HIGH-TECH SCIENCE CORPORATION, JSR CORPORATION, JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yoshihiro Koyama, Anto Yasaka, Tatsuya Shimoda, Yasuo Matsuki, Ryo Kawajiri
  • Patent number: 8518719
    Abstract: A method of manufacturing an organic electroluminescence device includes: preparing an organic EL device in which an anode, an organic layer including a luminescent layer, and a cathode formed of a transparent material are stacked in order and which has a shorted defective portion; irradiating the organic EL device with a laser beam from a direction of the cathode; measuring an intensity of radiated light from the organic EL device after the laser beam is absorbed through multiphoton absorption; changing a focal position of the laser beam in a stacking direction for performing the irradiating and measuring, and subsequently determining the focal position of the laser beam in the stacking direction such that the intensity of the radiated light is minimal; and irradiating the determined focal position with the laser beam, so as to solve a defect caused by the shorted defective portion.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 27, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomomi Hiraoka, Yasuo Segawa
  • Patent number: 8512817
    Abstract: A method of forming a lyophobic coating on a surface having oxidized groups is disclosed. The method includes bringing into contact with the surface a silane or siloxane having the formula SiX4 wherein each X is the same or different, wherein at least one X is a leaving group and at least one X is a lyophobic group.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 20, 2013
    Assignee: ASML Netherlands B.V.
    Inventor: Nina Vladimirovna Dziomkina
  • Publication number: 20130210170
    Abstract: A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Inventors: Yung-Fa CHOU, Ding-Ming KWAI
  • Publication number: 20130207086
    Abstract: A light emitting device includes an organic electroluminescent material having a glass transition temperature substantially at or below an intended normal operation temperature of the device. A method for regenerating an organic light emitting device by heating an electroluminescent layer to a temperature substantially equal to or above its glass transition temperature is also described. This provides a means and method for regenerating a degraded emitter in use.
    Type: Application
    Filed: June 16, 2011
    Publication date: August 15, 2013
    Applicant: Cambridge Display Technology Limited
    Inventors: Matthew Roberts, Andrew Lee
  • Patent number: 8501501
    Abstract: A sample with at least a first structure and a second structure is measured and a first model and a second model of the sample are generated. The first model models the first structure as an independent variable and models the second structure. The second model of the sample models the second structure as an independent variable. The measurement, the first model and the second model together to determine at least one desired parameter of the sample. For example, the first structure may be on a first layer and the second structure may be on a second layer that is under the first layer, and the processing of the sample may at least partially remove the first layer, wherein the second model models the first layer as having a thickness of zero.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Publication number: 20130196452
    Abstract: A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.
    Type: Application
    Filed: January 30, 2013
    Publication date: August 1, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8497150
    Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 30, 2013
    Assignee: Nexpower Technology Corp.
    Inventors: Yung-Yuan Chang, Hui-Chu Lin
  • Patent number: 8497140
    Abstract: An encapsulant layer for a photovoltaic module enabling recovering and recycling or reusing of reutilizeable resources such as a transparent front face substrate and photovoltaic cell and the like among constituents of a photovoltaic module, and a method for manufacturing a regenerated photovoltaic cell and a regenerated transparent front face substrate. The photovoltaic module is formed by laminating: a transparent front face substrate; a photovoltaic cell carrying a wiring electrode and a takeoff electrode, and an encapsulant layer is placed on at least one surface; and a rear face protecting sheet. The encapsulant layer is a separable layer formed mainly of a thermoplastic resin, and an output maintenance factor of photoelectronic power of the photovoltaic module using the encapsulant layer is in a range of 80% to 100%.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 30, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kasumi Ol, Takaki Miyachi, Isao Inoue, Koujiro Ohkawa, Hiroki Nakagawa
  • Patent number: 8492170
    Abstract: Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and silylation compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 23, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Kang Sub Yim, Thomas Nowak, Kelvin Chan
  • Patent number: 8492171
    Abstract: A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michel Deschenes, Marco Gauvin, Eric Giguère
  • Publication number: 20130176194
    Abstract: An organic light-emitting display apparatus includes a plurality of pixels, each defined by a scan line, a data line, and a power supply line, a plurality of control lines branching off of one wire in a first direction and simultaneously transferring control signals to the plurality of pixels; and a plurality of repair bridges placed between neighboring ones of the plurality of control lines, each of the plurality of repair bridges including a first bridge connected to one of the neighboring ones of the plurality of control lines and a second bridge connected to another one of the neighboring control lines.
    Type: Application
    Filed: August 20, 2012
    Publication date: July 11, 2013
    Inventors: Guang-Hai JIN, Jae-Beom CHOI, Kwan-Wook JUNG, June-Woo LEE, Seong-Jun KIM, Ga-Young KIM
  • Publication number: 20130167906
    Abstract: An organic photovoltaic module is disclosed, including a plurality of devices, wherein neighboring devices are separated by a gap, and each of the devices include a bottom electrode, a first carrier transporting layer, an active layer, a second carrier transporting layer and a top electrode. An insulating layer is disposed on the devices and filled into the gap, wherein the insulating layer includes a first opening exposing the bottom electrode and a second opening exposing the top electrode. A metal trace layer is filled into the first opening and the second opening to connect the devices in series or in parallel.
    Type: Application
    Filed: May 22, 2012
    Publication date: July 4, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mei-Ju Lee, Chao-Feng Sung
  • Publication number: 20130171744
    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.
    Type: Application
    Filed: December 14, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130161627
    Abstract: A photoelectric conversion apparatus includes: an active matrix-type TFT array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 27, 2013
    Inventors: Kenichi MIYAMOTO, Masami HAYASHI, Hideki NOGUCHI, Katsuaki MURAKAMI
  • Publication number: 20130155342
    Abstract: According to the present disclosure, there is disclosed an array substrate, a liquid crystal display panel and a broken-line repairing method thereof. The array substrate comprises: signal lines, which includes a plurality of gate lines and a plurality of data lines intersecting with each other; and a plurality of pixel units defined by the gate lines and the data lines, wherein a thin film transistor, a common electrode and a pixel electrode, which is connected to a drain of the thin film transistor, are formed in each of the pixel units, for each of the pixel units, at the positions of two corners which are adjacent to one of the data lines, a first repair area and a second repair area are formed, respectively; within the first repair area and the second repair area, patterns of the pixel electrode and the data line overlap, and there is no pattern of the common electrode.
    Type: Application
    Filed: August 1, 2012
    Publication date: June 20, 2013
    Applicants: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Song Wu
  • Publication number: 20130157386
    Abstract: A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.
    Type: Application
    Filed: February 6, 2013
    Publication date: June 20, 2013
    Applicant: SK HYNIX INC.
    Inventor: SK HYNIX INC.
  • Patent number: 8465991
    Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 18, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, Kevin M. McLaughlin, Bart van Schravendijk
  • Patent number: 8466386
    Abstract: A method of repairing a bonded metallic structure having a first metallic member bonded to a second metallic member is provided. The method includes the steps of: A) forming a hole in at least one of the first metallic member and second metallic member, wherein said hole is sufficiently configured to receive a slug; B) inserting said slug into said hole; and C) passing electrical current through said slug of sufficient intensity to promote melting at the interface between the first metallic member, second metallic member, and said slug, thereby securing the first metallic member with respect to the second metallic member. Alternately, the method may include: D) positioning said slug near said hole; E) passing electrical current through said slug of sufficient intensity to promote arcing between said slug and the bonded metallic structure; and F) inserting said slug into said hole thereby securing the first metallic member with respect to the second metallic member.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 18, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Pei-Chung Wang, John D. Fickes
  • Publication number: 20130149798
    Abstract: One object is to provide a method for manufacturing a display device in which shift of the threshold voltage of a thin film transistor including an oxide semiconductor layer can be suppressed even when ultraviolet light irradiation is performed in the process for manufacturing the display device. In the method for manufacturing a display device, ultraviolet light irradiation is performed at least once, a thin film transistor including an oxide semiconductor layer is used for a switching element, and heat treatment for repairing damage to the oxide semiconductor layer caused by the ultraviolet light irradiation is performed after all the steps of ultraviolet light irradiation are completed.
    Type: Application
    Filed: February 7, 2013
    Publication date: June 13, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 8455269
    Abstract: In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: June 4, 2013
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
  • Patent number: 8455268
    Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu