Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A method forms a gallium nitride crystal sheet. According to the method a metal melt, including gallium, is brought to a vacuum of 0.01 Pa or lower and is heated to a growth temperature of between approximately 860° C. and approximately 870° C. A nitrogen plasma is applied to the surface of the melt at a sub-atmospheric working pressure, until a gallium nitride crystal sheet is formed on top. Preferably, the growth temperature is of 863° C., and the working pressure is within the range of 0.05 Pa and 2.5 Pa. Application of the plasma includes introducing nitrogen gas to the metal melt at the working pressure, igniting the gas into plasma, directing the plasma to the surface of the metal melt, until gallium nitride crystals crystallize thereon, and maintaining the working pressure and the directed plasma until a gallium nitride crystal sheet is formed.

Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.

Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.

Abstract: One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group III-V material, which is thicker than the first layer and which has a second acceptor density, on top of the first layer in a second growing environment. In addition, the method comprises growing a third layer of p-type group III-V material, which is thinner than the second layer and which has a third acceptor density, on top of the second layer in a third growing environment.

Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.

Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.

Abstract: A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer.

Abstract: An electronic device includes a primary nanowire of a first conductivity type, and a secondary nanowire of a second conductivity type extending outwardly from the primary nanowire. A doped region of the second conductivity type extends from the secondary nanowire into at least a portion of the primary nanowire.

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Abstract: A metal oxide semiconductor field effect transistor includes a semiconductor substrate; a well region containing an impurity of a first conductivity type disposed on the semiconductor substrate, the well region including a source region and a drain region formed by adding an impurity of a second conductivity type, the source region and the drain region being separated from each other by a predetermined gap; an insulating film disposed on the surface of the well region in the gap between the source region and the drain region; and a gate electrode disposed on the insulating film. The well region is composed of an epitaxial layer, and the epitaxial layer includes an impurity layer of the first conductivity type having a different impurity concentration.

Abstract: The present invention discloses an integration flow of germanium into a conventional CMOS process, with improvements in performing selective area growth, and implementing electrical contacts to the germanium, in a way that has minimal impact on the preexisting transistor devices. The present invention also provides methods to integrate the germanium without impacting the optical or electrical performance of these devices, except where intended, such as in a germanium photodetector, or germanium waveguide photodetector.

Abstract: A semiconductor device and method for manufacturing the same. A cobalt silicide layer is placed on a silicon germanium layer through an MOCVD process, by forming a silicon germanium thin film on a first conductive type silicon substrate, implanting second conductive type impurities onto the silicon germanium thin film, and depositing a cobalt silicide (CoSi2) layer on the silicon germanium thin film, into which the second conductive type impurities are implanted, through a chemical vapor deposition (CVD) scheme.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.

Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved. The invention provides a manufacturing method for a semiconductor substrate with the steps of: forming a SiGe film on the top surface of a substrate having a silicon monocrystal layer in the (111) or (110) plane direction as the surface layer; introducing buried crystal defects into the above described substrate by carrying out ion implantation and annealing treatment; and forming a semiconductor film on the above described SiGe film.

Abstract: The invention relates to a method and device for depositing several crystalline semiconductor layers on at least one semiconductor crystalline substrate. According to said method, gaseous parent substances are introduced into a process chamber of a reactor by means of a gas inlet organ, said substances accumulating, optionally after a chemical gas phase and/or surface reaction, on the surface of a semiconductor substrate that is placed on a substrate holder in the process chamber, thus forming the semiconductor layer. Said semiconductor layer and the semiconductor substrate form a crystal consisting of either one or several elements from main group V, elements from main groups III and V, or elements from main groups II and VI.

Abstract: Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.

Abstract: Method of forming a lightly phosphorous doped silicon film. A substrate is provided. A process gas comprising a phosphorous source gas and a disilane gas is used to form a lightly phosphorous doped silicon film on the substrate. The diluted phosphorous source gas has a phosphorous concentration of 1%. The phosphorous source gas and the disilane gas have a flow ratio less than 1:100. The lightly phosphorous doped silicon film has a phosphorous doping concentration less than 1×1020 atoms/cm3.

Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm?3 at Al mole fractions up to 65% are obtained.

Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: The present invention provides a method of forming a semiconductor device that has a plurality of pin junctions comprising silicon films formed on a substrate by using a radio-frequency plasma CVD method, including: forming a first semiconductor layer; covering a surface of the first semiconductor layer with a member containing water with a content of 0.01 to 0.5 wt % so as to contact each other; removing the member; and forming a second semiconductor layer on the first semiconductor layer. According to the present invention, it is possible to efficiently form a semiconductor device having a multi-layer structure where a number of silicon thin films are laminated, to form a semiconductor device having less variation in characteristics among lots and having more excellent uniformity and characteristics, and to provide a semiconductor device excelling in adhesion and environmental resistance.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter. When a process gas is supplied to over a main surface of a silicon single crystal substrate 12 in rotation in almost parallel to the main surface thereof in one direction in a reaction chamber 10 through six inlet ports 18a to 18f disposed in width direction of the reaction chamber 10, H2 gas, a semiconductor raw material gas and a dopant gas are supplied onto an area in the vicinity of the center of the main surface of the silicon single crystal substrate 12 and an intermediate area thereof through the inner inlet ports 18a and 18b and the middle inlet ports 18c and 18d, and only H2 gas and the semiconductor raw material gas without the dopant gas are supplied onto an area in the vicinity of the outer periphery thereof from the outer inlet ports 18e and 18f.

Abstract: A highly reliable semiconductor laser device having a low operating voltage is obtained by increasing adhesive force of the overall electrode layer to a nitride-based semiconductor layer without deteriorating a low contact property. This nitride-based semiconductor laser device comprises a nitride-based semiconductor layer formed on an active layer and an electrode layer formed on the nitride-based semiconductor layer, while the electrode layer includes a first electrode layer containing a material having strong adhesive force to the nitride-based semiconductor layer and a second electrode layer, formed on the first electrode layer, having weaker adhesive force to the nitride-based semiconductor layer than the first electrode layer for reducing contact resistance of the electrode layer with respect to the nitride-based semiconductor layer.

Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.

Abstract: A volatile solid-source novel antimony precursor, Br2SbCH3, that may be utilized in semiconductor processing chambers for depositing antimony on a substrate by deposition methods, e.g., chemical vapor deposition, ion implantation, molecular beam epitaxy, diffusion and rapid thermal processing. The novel antimony compound of the invention is synthesized by combining tribromide antimony with trimethylantimony under heating conditions that form a Br2SbCH3 crystalline product.

Abstract: A method for producing a semiconductor device of the present invention includes: heating a first semiconductor layer made of a Group III nitride-based compound semiconductor in gas containing nitrogen atoms; and growing a second semiconductor layer made of a Group III nitride-based compound semiconductor on the first semiconductor layer.

Abstract: A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

Abstract: A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.

Abstract: A p-type InGaAlN layer, an InGaAlN active layer, and an n-type InGaAlN layer each having a composition represented by (AlxGa1-x)yIn1-yN (0≦x≦1, 0≦y≦1) are formed on a sapphire substrate. In the as-grown state, Mg is bonded to hydrogen atoms in the p-type InGaAlN layer. Then, the back surface of the sapphire substrate is irradiated with a laser beam in a nitrogen atmosphere. The resistance of the p-type InGaAlN layer is reduced by removing hydrogen therefrom with irradiation with a weak laser beam. During the irradiation with the laser beam, the diffusion of a dopant in a multilayer portion is suppressed such that a dopant profile retains sharpness. It is also possible to separate the sapphire substrate from the multilayer portion by subsequently using an intense laser beam for irradiation.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: An improved atomic layer doping apparatus is disclosed as having multiple doping regions in which individual monolayer species are first deposited and then dopant atoms contained therein are diffused into the substrate. Each doping region is chemically separated from adjacent doping regions. A loading assembly is programmed to follow pre-defined transfer sequences for moving semiconductor substrates into and out of the respective adjacent doping regions. According to the number of doping regions provided, a plurality of substrates could be simultaneously processed and run through the cycle of doping regions until a desired doping profile is obtained.

Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

Abstract: A stacked silicon gate structure for a MOSFET may be formed in a CVD chamber. The stacked structure includes a first polycrystalline silicon layer, a microcrystalline layer, and second polycrystalline silicon layer. The microcrystalline layer has a randomly orientated crystal structure with a smaller average crystal grain size than the first and second polycrystalline silicon layers. The microcrystalline layer is capable of maintaining its original crystal structure even while undergoing high temperature process substantially without further recrystallization. This allows the microcrystalline layer to suppress migration of dopants in the second polycrystalline silicon layer into the first polycrystalline silicon layer and thereby prevent a shift in the threshold voltage that would otherwise result from such dopant penetration.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: First, the substrate temperature is set to 1020° C., and an n-type cladding layer (14) made of n-type Al0.1Ga0.9N, an n-type optical guide layer (15) made of n-type GaN, and a flatness maintenance layer (16) made of n-type Al0.2Ga0.8N for maintaining the surface flatness of the n-type optical guide layer (15) by suppressing re-evaporation of the constituent atoms of the n-type optical guide layer (15), are grown in this order on a substrate (11) made of sapphire. Then, the supply of a group III material gas is stopped, the substrate temperature is decreased to 780° C., and the carrier gas is switched from a hydrogen gas to a nitrogen gas. Then, an active layer (17) having a multiple quantum well structure is grown by introducing NH3 as a group V source and selectively introducing TMI and TMG as a group III source.

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.

Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.

Abstract: A method is described for safe gas phase doping a semiconductor with arsenic. The substrate including a semiconductor structure is exposed to arsine at elevated temperatures within a reaction chamber. Thereafter, prior to opening the reaction chamber, a sealant layer is formed over the semiconductor structure. The sealant layer inhibits outdiffusion of arsenic when the substrate is unloaded from the reaction chamber, enabling safe unloading at relatively high temperatures. In the illustrated embodiments, the sealant layer can be formed by oxidation, nitridation or chemical vapor deposition. Forming the sealant layer can be conducted prior to, during or after cooling the substrate to an unloading temperature. Preferably, a gettering step is conducted after gas phase doping and prior to forming the sealant layer, such as by exposing the substrate to HCl vapor.

Abstract: A microroughness on a surface is produced in a single process step by forming semiconductor grains directly from a process gas. The semiconductor grains are finely distributed on the surface. As a result of forming the microroughness in a single process step, time and costs are saved during fabrication.

Abstract: A process for fabricating a structure including a carrier substrate and a layer of semiconductor material on one surface of the carrier substrate. The process a) forms a layer of semiconductor material on one surface of a first substrate, b) forms a cleavage zone in the first substrate, which delimits a superficial layer, c) transfers the first substrate, with the layer of semiconductor material, onto the carrier substrate, d) provides energy to cause cleavage of the first substrate along the cleavage zone, and e) removes said superficial layer to uncover the layer of semiconductor material.

Abstract: A method of producing a Schottky varicap (25) including: (a) providing an epitaxial layer (12) on a semiconductor substrate (1); (b) providing an insulating layer including an oxide layer and a nitride layer on a predetermined area of the surface of the epitaxial layer (12); (c) depositing a polysilicon layer (6); (d) applying a first high temperature step to diffuse a guard ring (10) around the first predetermined area; (e) removing a predetermined portion of the polysilicon layer (6) to expose the first silicon nitride film (5); (f) implanting atoms through at least the first oxide film (4) to provide a predetermined varicap doping profile; (g) applying a second high temperature step to anneal and activate the varicap doping profile; (h) removing the first oxide film (4) to provide an exposed area; (i) providing a Schottky electrode (17) on the exposed area.

Abstract: The present invention relates to a method of crystallizing a silicon film, a thin film transistor, and a fabricating method thereof using the same. More particularly, the present invention relates forming a crystalline silicon film by crystallizing a silicon film using laser energy, and a thin film transistor and a fabricating method thereof using the same. The present invention includes forming a buffer layer on a substrate and forming an amorphous silicon film on the buffer layer wherein the amorphous silicon film includes a first region and second regions connected to both ends of the first region. The buffer layer is etched to a degree by using the amorphous silicon as a mask, wherein a space is formed under the first region and a central part of the second region contacts a remaining portion of the buffer layer. The amorphous silicon film is then crystallized.

Abstract: A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.

Abstract: A gallium-nitride-based blue light emitting element that is manufacturable through a small number of processes and a method of manufacturing the same are disclosed. A first gallium-nitride-based semiconductor layer containing impurities of a first conductivity type, a gallium-nitridebased semiconductor active layer that is substantially intrinsic, and a second gallium-nitride-based semiconductor layer containing impurities of a second conductivity type that is opposite to the first conductivity type are formed according to a thermal CVD method and are left in an inert gas to cool by themselves.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.