Abstract: A method of growing a p-type doped Group II-VI semiconductor film includes the steps of forming a lattice comprising a Group II material and a Group VI material wherein a cation-rich condition is established at a surface of the lattice. The method further includes the steps of generating an elemental Group V flux by evaporating an elemental Group V material and providing the elemental Group V flux to a Group VI sublattice of the lattice.

Abstract: In a silicon conductor doped with an impurity of 100 nm or less thick, a method is provided for manufacturing a silicon thin film conductive element which can prevent the increase of resistance with a low impurity concentration. The method includes the step in which, after the formation of an impurity-containing amorphous silicon film, a crystallization is performed without removing the film from a film forming device by performing a heat treatment while flowing a gas containing the impurity.

Abstract: A semiconductor substrate has a support substrate formed of monocrystal silicon, an oxide film formed on the support substrate and a thin film of monocrystal silicon formed on the oxide film. The support substrate is a high-concentration P-type substrate to which boron is so doped that a resistivity of the support base is 0.1 .OMEGA..cm or less. In manufacturing: boron is into the support base so that a resistivity of the support base is 0.1 .OMEGA..cm or less; a silicon substrate on which the thin film of monocrystal silicon is formed is heated at 1100.degree. C. or higher for 30 min or longer within a reducing atmosphere; the heat treated silicon substrate is attached to the high-concentration P-type support substrate via the oxide film formed on a surface of any one of the support substrate and the P-type silicon substrate and the attached substrates are heated at 950.degree. C. or higher for 10 min or longer to bond the attached substrates together; and the bonded silicon substrate is thinned.

Abstract: In a bipolar transistor and the manufacturing method thereof, the bipolar transistor includes a first conductive well, an emitter impurity layer formed in the center of the well, a base impurity layer formed in the form of completely surrounding the emitter impurity layer, and a first conductive high-concentration collector impurity layer having an annular shape along the edge of the well, and maintaining a constant interval from the base impurity layer. The first conductive layer formed to be parallel with the high-concentration collector impurity layer is connected therewith through a contact hole, and is connected with the collector electrode through another contact hole. Owing to a simple manufacturing process, the processing time and cost can be reduced. Also, parasitic bipolar transistors are not generated nor is increased collector resistance produced, thereby increasing reliability.

Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

Abstract: The present invention provides a method for depositing polycrystal Si films, including n-type and p-type polycrystal Si films, using a material gas, a doping gas, and hydrogen gas. This method comprises a film-forming time-period having:(a) a time-period for depositing a film;(b) a time-period for diffusing dopants in the deposited film; and(c) a time-period for treating the film surface with hydrogen plasma. According to this method, an n-type or p-type polycrystal Si film with excellent crystallinity can be provided using the material gas and the doping gas. Further, this method is able to proceed at a low temperature and achieve satisfactory structural relaxation of the resulting film.

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract: A method of manufacturing a semiconductor device, in which a pn-junction (2) is provided in a semiconductor wafer (1) of a first conduction type by providing doping atoms of a second conduction type, which is opposed to the first conduction type, via a first main face (3) of the main faces (3, 5) of the wafer (1), subdividing said wafer (1) into individual semiconductor bodies (10) having a pn-junction (2) between and substantially parallel to two opposing connection faces (3, 5), connecting said connection faces (3, 5) to connection bodies (11, 12) by means of a connection layer (15) and covering the semiconductor bodies (10) with a glass (20) A glass-covered semiconductor device is also described. After the pn-junction (2) has been provided on the first main face (3) of the semiconductor wafer (1), a monocrystalline silicon layer (7) having atoms of the second conduction type is epitaxially provided, whereafter the wafer (1) is subdivided into semiconductor bodies (10).

Abstract: The specification describes a process for growing device quality III-V heteroepitaxial layers without the use of buffer layers, i.e. largely defect free layers with thicknesses greater than 50 Angstroms directly on the III-V substrate. These high quality heteroepitaxial layers are grown by low temperature MBE.

Abstract: A method of manufacturing a p-type III-V nitride compound semiconductor utilizing vapor phase epitaxy is carried out in a MOCVD reactor by growing a III-V nitride compound semiconductor in the reactor employing a reaction gas containing a p-type impurity and then annealing in-situ the nitride compound semiconductor to bring about acceptor activation, the annealing carried out at a temperature below the growth temperature of the III-V nitride compound semiconductor during reactor cooldown. A nitrogen (N) reactant or precursor is provided in the reactor during the annealing step which can produce a reactive form of N capable of suppressing surface decomposition and does not produce atomic hydrogen. Also, acceptor activation is achieved through the employment of a cap layer comprising a n-type Group III-V nitride material, e.g., n-GaN, grown on the p-doped Group III-V nitride layer preventing the occurrence of hydrogenation of the underlying p-doped layer during cooldown.

Abstract: The invention relates to a method of manufacturing a semiconductor device with a pn junction, whereby an epitaxial layer (2) with a first zone (3) of a first conductivity type and with a second zone (4) of a second conductivity type opposed to the first is provided on a silicon substrate (1), a pn junction (5) being formed between the second and first zones (3, 4, respectively). According to the invention, the method is characterized in that the epitaxial layer (2) is provided by means of a CVD process at a temperature below 800.degree. C., the epitaxial layer (2) being provided in that first the first zone (3) and then the second zone (4) are epitaxially provided on the substrate (1), while no heat treatments at temperatures above 800.degree. C. take place after the epitaxial layer (2) has been provided.

Abstract: Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.

Abstract: Growth of doped gallium nitride, especially p-type gallium nitride, without using post-growth processing is achieved by eliminating hydrogen containing molecules from the growth process before cooling down the substrate. Rapid cooling of the substrate with nitrogen gas prevents the reaction of p-type dopant atoms with hydrogen, and the use of the nitrogen gas also keeps the nitrogen intact within the crystalline structure.

Abstract: Polycrystalline silicon-germanium alloy is grown on a glass substrate through a chemical vapor deposition under the conditions where the substrate temperature ranges from 350 degrees to 450 degrees in centigrade, the ratio between gas flow rate of Si.sub.2 H.sub.6 and the gas flow rate of GeF.sub.4 ranges from 20:0.9 to 40:0.9 and the dilution gas is selected from the group consisting of helium, argon, nitrogen and hydrogen, and the composition ratio of silicon of the polycrystalline silicon-germanium is equal to or greater than 80 percent so that the carrier mobility is drastically improved.

Abstract: The present invention relates to an epitaxial wafer including a PN junction, which is improved in terms of light output and can have a good-enough ohmic electrode formed thereon. Epitaxial layers are formed of GaAs.sub.1-x P.sub.x where 0.45 <.times..ltoreq.1). A first P-type layer is formed by a vapor-phase growth process, and a second P-type layer is formed on the first P-type layer by a thermal diffusion process, said second P-type layer having a carrier concentration higher than that of said first P-type layer.

Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.

Abstract: A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.

Abstract: The invention relates to a method for manufacturing a III-V system compound semiconductor device, provides such a new C dopant as alkyl halide (CH.sub.2 I.sub.2 for example) containing carbon (C), iodine (I), and hydrogen (H) for giving a highly p-type conductivity to a GaAs crystal layer, an InGaAs crystal layer or the like as an object of it, and includes a process of forming a p-type III-V system compound semiconductor layer as using a compound containing carbon (C) as a dopant material for giving a p-type conductivity and further containing iodine (I) and hydrogen (H) as impurity.