Ordering Or Disordering Patents (Class 438/511)
  • Patent number: 6255122
    Abstract: High-capacity capacitors and gate insulators exhibiting moderately high dielectric constants with surprisingly low leakage using amorphous or low temperature films of perovskite type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, a niobate, aluminate or tantalate system material such as lead magnesium niobate, lithium niobate lithium tantalate, potassium niobate and potassium tantalum niobate, a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate, and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate deposited directly on a silicon surface at temperatures about 450° C. or less.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: July 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter Richard Duncombe, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Thomas McCarroll Shaw
  • Patent number: 6232208
    Abstract: A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to form the gate electrode, to reduce gate depletion. The doped gate electrode layer is then patterned to form a gate electrode having a substantially rectangular profile.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: May 15, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Wu, Dong-Hyuk Ju
  • Patent number: 6168981
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 2, 2001
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 5993538
    Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: November 30, 1999
    Assignee: Mega Chips Corporation
    Inventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama