Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.

Abstract: A semiconductor memory device includes conductive films and insulating layers alternately stacked on a substrate, substantially vertical channel layers penetrating the conductive films and the insulating layers, multilayer films including a charge storage film interposed between the conductive films and the substantially vertical channel layers, and a first anti-diffusion film formed on etched surfaces of the conductive films.

Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.

Abstract: The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.

Abstract: A method for manufacturing a memory element is proposed. A laser beam emitted from a laser oscillator is entered into a deflector, and a laser beam which has passed through the deflector is entered into a diffractive optical element to be diverged into a plurality of laser beams. Then, a photoresist formed over an insulating film is irradiated with the laser beam which is made to diverge into the plurality of laser beams, and the photoresist irradiated with the laser beam is developed so as to selectively etch the insulating film.

Abstract: A semiconductor device includes a semiconductor substrate; a gate dielectric layer disposed on the semiconductor substrate; a gate conductive layer doped with impurities selected from nitrogen, carbon, silicon, germanium, fluorine, oxygen, helium, neon, xenon or a combination thereof on the gate dielectric layer; and source/drain doped regions formed adjacent to the gate conductive layer in the semiconductor substrate, wherein the source and drain doped regions are substantially free of the impurities doped into the gate conductive layer. These impurities reduce the diffusion rates of the N-type of P-type dopants in the gate conductive layer, thereby improving the device performance.

Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.

Abstract: A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.

Abstract: Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

Abstract: The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack.

Abstract: In a replacement metal gate process flow, sacrificial gates are exposed and removed subsequent to the formation of source and drain regions for various transistor devices. Sidewalls formed adjacent to the sacrificial gates remain. By using an angled implant such that, for a short-channel device, the remaining sidewalls shadow and protect the exposed short-channel region, a designer may adjust the threshold voltage on long-channel devices without affecting the threshold voltage of the short-channel device.

Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.

Abstract: An improved method of tilting a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. The mask and substrate are tilted at a first angle relative to the incoming ion beam. After the substrate is exposed to the ion beam, the mask and substrate are tilted at a second angle relative to the ion beam and a subsequent implant step is performed. Through the selection of the aperture size and shape, the cross-section of the mask, the distance between the mask and the substrate and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract: A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.

Abstract: A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

Abstract: A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.

Abstract: An improved method of doping a workpiece is disclosed. In this method, a film comprising the species to be implanted is introduced to the surface of a planar or three-dimensional workpiece. This film can be grown using CVD, a bath or other means. The workpiece with the film is then subjected to ion bombardment to help drive the dopant into the workpiece. This ion bombardment is performed at elevated temperatures to reduce crystal damage and create a more abrupt doped region.

Abstract: A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation region formed in a portion of the substrate structure below the spacers filled between the third and fourth gate electrodes, and second ion implantation regions formed in portions of the substrate structure exposed between the spacers, the second ion implantation regions having a higher concentration than the first ion implantation region.

Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.

Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the least one of the at least one of the gate structures.

Abstract: Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers laterally adjacent the gate stack. The method further includes the steps of amorphizing the S/D regions, depositing a silicide-forming material over the amorphized S/D regions, and heating the partially-completed semiconductor device to a predetermined temperature at which the silicide-forming material reacts with the amorphized S/D regions.

Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for suppressing punch-through will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for adjusting the threshold voltage of a cell will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region on a semiconductor substrate. A well will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Abstract: Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

Abstract: A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.

Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.

Abstract: The invention provides a method of manufacturing a semiconductor device at low cost in which the gate insulation film having a trench structure is not damaged by arsenic ions when the emitter layer or the like is formed and the insulation breakdown voltage is enhanced. A gate electrode made of polysilicon formed in a trench is thermally oxidized in a high temperature furnace or the like to form a thick polysilicon thermal oxide film on the gate electrode. Impurity ions are then ion-implanted to form an N type semiconductor layer that is to be an emitter layer or the like. At this time, the polysilicon thermal oxide film is formed thicker than the projected range Rp of impurity ions in the silicon oxide film for forming the N type semiconductor layer as the emitter layer or the like by ion implantation. This prevents a gate insulation film between the gate electrode and the N type semiconductor layer from being damaged by the impurity ions.

Abstract: Some embodiments discussed relate to an integrated circuit and methods for making it. In an example, a method can include providing a semiconductor wafer including a fin, and introducing a noise-reducing dopant into a sidewall of the fin.

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

Abstract: A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.

Abstract: An example method of forming a pinned photodiode includes applying a photoresist mask to a semiconductor layer at a location where a transfer gate will subsequently be formed. First dopant ions are then implanted at a first angle to form a first dopant region under an edge of the photoresist mask. Next, a photoresist mask is etched such that a thickness of the photoresist mask is reduced to form a trimmed photoresist mask. Second dopant ions are then implanted at a second angle to form a second dopant region, wherein the second dopant ions are shadowed by the trimmed photoresist mask to exclude the second dopant ions from a region partially above the first dopant region and adjacent to an edge of the trimmed photoresist mask.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for exposing a region of a semiconductor substrate. Dopant ions are implanted into the exposed region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.