Abstract: A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.

Abstract: In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain region. The N-type diffusion layer is diffused in a ? shape at least below the gate electrode. With the structure described above, a diffusion region of the N-type diffusion layer expands and comes to be a low-concentration region in the vicinity of a surface of an epitaxial layer. Thus, it is possible to reduce an electric field from the gate electrode and an electric field between a source and a drain.

Abstract: An approach for providing a cleave initiation using a varying ion implant dose is described. In one embodiment, there is a method of forming a substrate. In this embodiment, a semiconductor material is provided and implanted with a spatially varying dose of one or more ion species. A handler substrate is attached to the implanted semiconductor material.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: The present invention provides a method of producing an SOI wafer, comprising at least steps of forming an oxygen ion-implanted layer by implanting oxygen ions into a silicon wafer from one main surface thereof, subjecting the silicon wafer to oxide film-forming heat treatment to convert the oxygen ion-implanted layer into a buried oxide film, and thereby producing an SOI wafer having an SOI layer on the buried oxide film, wherein when the buried oxide film is formed in the silicon wafer, the buried oxide film is formed so that a thickness thereof is thicker than a thickness of the buried oxide film which the SOI wafer to be produced has, and thereafter the silicon wafer in which the thicker buried oxide film is formed is subjected to a heat treatment to reduce the thickness of the buried oxide film.

Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.

Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.

Abstract: A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

Abstract: A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 ? or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 ? or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

Abstract: A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

Abstract: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type.

Abstract: A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by the opening. Thereafter, a second insulating layer is formed on the substrate to fill the opening. The second insulating layer together with the first insulation layer form a third insulating layer. The third insulating layer is patterned to form an isolation layer that exposes the substrate and the buried doped region. The isolation layer extends in a second direction and crosses over the first direction. A semiconductor layer is formed on the substrate to fill the areas on the respective sides of the isolation layer.

Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.

Abstract: A method for manufacturing a solid state imaging device includes steps of forming a photodiode layer buried in a semiconductor substrate by ion injection and of forming a shielding layer buried in the photodiode layer by ion injection. At least in the ion injection process in the step of forming the shielding layer, an ion injection pause period is provided at least one time during whole ion injection step. According to the method, crystal defects are prevented from generating even if ion injection is performed with high energy, thereby suppressing dark current without complexity in manufacturing process.

Abstract: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.

Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.

Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

Abstract: A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first material type. The structure includes a first structure and a buried channel.

Abstract: In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the separatory ion implanted layer formation step is adjusted through energy of the ion implantation. Dose of the ion implantation is set smaller as the depth of formation measured from the first main surface J becomes smaller. A smaller dose results in a smaller surface roughness of the separation surface, and makes it possible to reduce polishing stock removal of the separation surface of the bonded silicon single crystal film in the planarization step. Uniformity in the thickness of the SOI layer can consequently be improved even for the case where a thin SOI layer has to be formed.

Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

Abstract: The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said layer of said first semiconductor material in said substrate, said buried layer having an upper surface and a lower surface and dividing said substrate into an upper part and a lower part; creating a buried damage layer; which at least partly adjoins and/or partly includes said upper surface of said buried layer; and removing said upper part of said substrate and said buried damage layer for exposing said buried layer. The invention also provides a corresponding layered semiconductor structure.

Abstract: A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.

Abstract: Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate to define an active region. A source region, a buried N+ region and a drain region are serially disposed at the active region. A memory gate is disposed to cross-over the buried N+ region. A first channel region is formed between the source region and the buried N+ region. A tunnel region is located between the buried N+ region and the memory gate and self-aligned with the buried N+ region.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion region.

Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

Abstract: A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment step of maintaining the wafer in an oxygen contained atmosphere at a temperature that is not lower than 1300° C. but less than a silicon melting point for 6 to 36 hours to change the first and the second ion-implanted layers into a BOX layer, a gas containing chlorine that is not less than 0.1 volume % but less than 1.0 volume % is mixed into an atmosphere during temperature elevation in the high-temperature heat treatment.

Abstract: A complementary metal oxide semiconductor image sensor and a method for fabricating the same are disclosed, wherein a width of a depletion area of a photodiode is varied by variably applying a back bias voltage to a semiconductor substrate without using any color filter, thereby preventing a back bias voltage from influencing a transistor formed on the outside of a photodiode in a CMOS image sensor sensing optical color sensitivity of light rays irradiated to the photodiode.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

Abstract: The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

Abstract: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantation is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved. The invention provides a manufacturing method for a semiconductor substrate with the steps of: forming a SiGe film on the top surface of a substrate having a silicon monocrystal layer in the (111) or (110) plane direction as the surface layer; introducing buried crystal defects into the above described substrate by carrying out ion implantation and annealing treatment; and forming a semiconductor film on the above described SiGe film.

Abstract: Method for making a semiconductor structure is proposed. It comprises the steps: —providing a base layer (10) having a first lattice constant, —forming buried islands on the base layer (10) having a second lattice constant that is smaller or larger than the first lattice constant, —at least partially covering the base layer (10) and the buried islands with a cover layer (14), whereby the cover layer (14) has a locally increased or reduced lattice constant in areas above the buried islands, —growing small islands (15) on the areas of the cover layer (14) with locally increased or reduced lattice constant, —depositing a thin layer (16) at least partially covering the cover layer (14) and the small islands (15), —at least partially removing the small islands (15) to provide for an opening (17) being positioned exactly above the buried islands.

Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer contains hydrogen mostly in form of hydrogen platelets oriented in parallel to each other and to neighboring crystal surface. The fragile layer is preferably grown within a single crystalline silicon wafer to facilitate the detachment of an overlaying thin layer of single crystalline silicon from the initial wafer. The hydrogen layer is grown on a seed layer. The seed layer is preferably formed by ion implantation of inert gases at doses in 1015 cm?2 range. The hydrogen layer is grown by plasma hydrogenation of the substrate. The hydrogenation process begins at substrate temperature not exceeding 250° C., and than continues at higher temperature not exceeding 400° C.

Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.

Abstract: The present invention provides a method and apparatus for lift-off of a thin layer from a crystalline substrate, preferably the layer from a silicon wafer to further form a silicon-on-insulator (SOI) sandwich structure, wherein a separation layer is formed inside a donor wafer by trapping hydrogen into a preformed, buried defect-rich layer preferably obtained by implanting a low dose of light ions through a protective layer deeply into this donor wafer. The donor wafer is then bonded to a second wafer and then split at the separation layer using a splicing apparatus. The invention also provides a “Wide Area Ion Source” (WAIS) that performs both implants in a very cost effective manner.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Abstract: A buried channel CMOS imager having an improved signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate. The buried channel CMOS imager thus exhibits a better signal-to-noise ratio. Also disclosed are processes for forming the buried channel CMOS imager.