Abstract: A SOI substrate includes a SiO2 film (230) having a center located at the depth of the damage peak where the crystal damage is maximum after the Si substrate (10) is ion-implanted with oxygen ions. Even if a crystal defect (240) remains at the depth of the density peak where the density is maximum, the crystal defect does not effect the device operation because it is outside the active layer. By using a low-dose SIMOX process, a lower-cost SOI substrate can be obtained wherein crystal defects formed in the active layer are reduced.

Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not

Abstract: A first mask which is formed which exposes a cell array region and a peripheral circuit region of a semiconductor substrate. The cell array region and the peripheral circuit region are of a same conductive MOS type. Then, a preceding ion implantation process is implemented in both the cell array region and the peripheral circuit region utilizing the first mask. The preceding ion implantation process has ion implantation parameters corresponding to first implantation design specifications of one of the cell array region and the peripheral circuit region. Then, a second mask is formed which shields the one of the cell array region and the peripheral circuit region and which exposes the other of the cell array region and the peripheral circuit region. A subsequent ion implantation process is then implemented in the other of the cell array region and the peripheral circuit region utilizing the second mask.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Abstract: Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

Abstract: Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

Abstract: A method for forming a junction in a semiconductor device including the steps of: forming a photoresist film pattern on a semiconductor substrate excluding a halo implant region; performing a first halo implant process on the halo implant region of the semiconductor substrate by using a tilt angle of about 45°; and performing a second halo implant process on the halo implant region of the semiconductor substrate by using a tilt angle of about 0°.

Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

Abstract: Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.

Abstract: The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A semiconductor device of planar structure has a pn-junction (10) formed by a first layer (1) doped according to a first conductivity type, n or p, and on top thereof a second layer (2) doped according to a second conductivity type. The second layer has a higher doping concentration than the first layer and a lateral edge thereof is provided with an edge termination with second zones of said second conductivity type separated by first zones (4) of said first conductivity type arranged so that the total charge and/or the effective sheet charge density of dopants according to said second conductivity type is decreasing towards the laterally outer border (8) of the edge termination. A third layer (5) doped according to said first conductivity type is arranged on top of said second layer at least in the region of the edge termination for burying the edge termination of the device thereunder.

Abstract: A structure comprising a thin layer (2) that can be integral with a support (3), the thin layer being a layer of a semiconductor material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer (2). A method of manufacturing such a structure is also disclosed.

Abstract: A transistor device suitable for high voltage and low voltage applications, while maintaining minimum channel lengths. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.

Abstract: A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.

Abstract: The present invention includes a method of forming a capacitor on a semiconductor support wafer. The method comprises forming a diffusion area in the support wafer to provide a first electrode and a second electrode of the capacitor, implanting a first gas in the diffusion area to form a dielectric layer at a predetermined depth, wherein a first region of the diffusion area is formed below the dielectric layer as the first electrode of the capacitor and a second region of the diffusion area is formed above the dielectric layer as the second electrode of the capacitor, etching a trench in the support wafer to isolate laterally the dielectric layer, growing an epitaxial layer, and implanting a second gas to isolate the epitaxial layer from the second electrode. The capacitor is formed substantially subjacent a semiconductor device formed in the epitaxial layer.

Abstract: Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A semiconductor device is provided, which prevents the development of localized breakdowns at the semiconductor sidewall, having a stabilized, desired breakdown voltage. It embraces a p-type third semiconductor region formed on a first main surface of an n-type semiconductor body; an n-type second semiconductor region selectively formed at the center of a second main surface; an n-type first semiconductor region formed between the third and the second semiconductor regions; and, n-type fourth semiconductor region surrounding the first and the second semiconductor regions. The impurity concentration of the first semiconductor region is set higher than that of the fourth semiconductor region.

Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: A method for implanting ions into a surface of a semiconductor structure covered by a layer of insulating material, for example into a trench wall covered by a layer of oxide. A beam of ions is directed at a glancing angle to the layer of insulating material such that a substantial proportion of ions which are implanted into the semiconductor structure surface are scattered from the beam by the layer of insulating material. It is possible therefore to implant ions into a trench wall without requiring a beam source arranged to deliver a beam at a large angle to the trench wall surface.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: A method of producing an SOI substrate is disclosed which comprises a step of preparing an Si substrate prepared by the floating zone process (FZ process), a step of implanting oxygen ions from the principal surface side of the Si substrate thereinto to form an ion-implanted layer in the Si substrate, and a buried Si oxide layer forming step of forming an Si oxide layer buried below the single-crystal Si layer on the principal surface side, by a heat treatment of the Si substrate.

Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to fabricate an N-well after a pad oxide layer and a silicon nitride layer is formed. After a thick field oxide is formed by using a high temperature steam oxidation process, another high energy and low dose multiple boron implantation is then performed to fabricate a buried heavily boron doped region. A rapid thermal processing (RTP) system is following used to activate the boron dopant to form buried p+ layer and to recover the implanted damages. All the field oxide films are then removed by using a diluted HF or BOE solution. After porous silicon is obtained via anodic electrochemical dissolution in the HF solution, the porous silicon is then thermally oxidized to form the separate n-type silicon islands. Next, a thick CVD oxide film is deposited and then etched back to planarize device surface.

Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

Abstract: A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal defects resulting from the implantation; depositing an epitaxial layer; digging trenches delimiting each implanted region; and annealing the buried layers, the lateral diffusion of which is blocked by said trenches, said trenches being deeper than the downward extension of the diffusions resulting from said implantations.

Abstract: A method for fabricating an ultra-shallow semiconductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: A single-crystal silicon substrate having a surface layer which has been heat-treated in a reducing atmosphere containing hydrogen is prepared. An ion-implantation layer is formed by implanting oxygen ions. Subsequently, a buried oxide film (BOX) layer is formed by a desired heat-treatment utilizing the ion-implantation layer. An SOI substrate having a single-crystal silicon layer (SOI layer) which is formed on the BOX layer and has a remarkably reduced number of defects such as COPs is obtained.

Abstract: A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

Abstract: The invention relates to a method of manufacturing a thin film of solid material comprising at least the following steps: a step of ionic implantation through one face of a substrate of said solid materials using ions capable of creating in the volume of the substrate and at a depth close to the mean depth of penetration of the ions, a layer of micro-cavities or micro-bubbles, this step being carried out at a particular temperature and for a particular length of time, an annealing step intended to bring the layer of micro-cavities or micro-bubbles to a particular temperature and for a particular length of time with the intention of obtaining cleavage of the substrate on both sides of the layer of micro-cavities or micro-bubbles. The annealing step is carried out to a thermal budget made in relation to the thermal budget of the ionic implantation step and possibly other thermal budgets inferred for other steps, in order to provide said cleavage of the substrate.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A technique for forming a film of material having active devices from a donor substrate. The technique has a step of introducing energetic particles in a selected manner through a surface and active devices of a donor substrate a selected depth underneath the active devices, where the particles have a relatively high concentration to define a donor substrate material above the selected depth. The surface of the donor substrate is attached to a release layer on a transfer substrate. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate at the selected depth, whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate. The transfer substrate holds the cleaved material and is used to transfer the cleaved material with active devices onto a target substrate.

Abstract: A multilayercd substrate. The substrate has a plurality of particles defined in a pattern in the substrate at a selected depth underneath the surface of the substrate. The particles are at a concentration at the selected depth to define a substrate material to be removed above the selected depth. The substrate material is removed after forming active devices on the substrate material using, for example, conventional semiconductor processing techniques. The pattern is defined in a manner to substantially prevent a possibility of detachment of the substrate material to be removed during conventional thermal processes of greater than about room temperature or greater than about 200 degrees Celsius.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact between the floating diffusion region and the gate of a source follower output transistor. The buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a buried contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region on, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method is provided for forming a multiple well of a semiconductor device is provided. By this method, a pocket well region of a first conductivity type is formed over a predetermined first region of a semiconductor substrate of a first conductivity type, using a first photolithography process. A first deep well region of a second conductivity type is then formed under the pocket well region in a self-aligned manner. A peripheral well region of the first conductivity type is selectively formed in a predetermined second region of the semiconductor substrate apart from the pocket well region, using a second photolithography process.

Abstract: A method for forming a plurality of buried layers inside a semiconductor device is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Then, the first type p+-type ions are implanted into the semiconductor substrate to form the p+-type region under the surface of semiconductor substrate. The semiconductor substrate is etched to form a plurality of concave portions and a plurality of convex portions using the first photoresist. The n+-type ions are second implanted into the semiconductor substrate as a plurality of n+-type region. Next, the oxide layer is deposited over the surface of the plurality of concave portions and the surface of the plurality of convex portions. The plurality of n+-type regions are heated to form as the buried layers. The oxide layer is removed. Finally, a silicon layer is formed to fill the plurality of concave of portions a silicon layer and to cover the surface of the plurality of convex portions.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.