By Application Of Corpuscular Or Electromagnetic Radiation (e.g., Electron, Laser, Etc.) Patents (Class 438/535)
  • Patent number: 11333913
    Abstract: A liquid crystal device comprises a first polymer substrate, a first buffer layer, thin film transistors, a liquid crystal layer and a second polymer substrate. The first buffer layer is disposed on the first polymer substrate. The thin film transistors are disposed on the first buffer layer. The liquid crystal layer is disposed on the thin film transistors. The second polymer substrate is disposed on the liquid crystal layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 17, 2022
    Assignee: InnoLux Corporation
    Inventors: Yu-Chih Tseng, Kuo-Shun Tsai, Chuan-Ming Yeh, Chu-Hong Lai, Ker-Yih Kao
  • Patent number: 10910406
    Abstract: A display apparatus includes a substrate including a polymer resin. A portion of the substrate including an upper surface of the substrate is doped with 1×1020 to 1×1023 dopants per 1 cm3. A barrier layer is positioned above the upper surface of the substrate. A buffer layer is positioned above the barrier layer. A thin film transistor is positioned above the buffer layer. A display device is electrically connected to the thin film transistor.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaewoo Jeong, Taewook Kang, Jongoh Seo, Byungsoo So
  • Patent number: 10157995
    Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Hong-Mao Lee, Huicheng Chang
  • Patent number: 9937361
    Abstract: In a particle beam irradiation apparatus that controls a scanning apparatus so that each irradiation position is irradiated with a particle beam a rescan-count number of times by repeating for the rescan-count number of times the irradiation of all irradiation positions in the irradiation target, the irradiation apparatus includes a calculator that receives either one of a rescan count n or a beam intensity J that is a particle beam dose per unit time, to calculate a maximum value of the other satisfying the following conditional expression (P1) for all irradiation positions to present the maximum value to a user.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: April 10, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Sakamoto, Yuehu Pu, Hisashi Harada, Taizo Honda
  • Patent number: 9201245
    Abstract: An optical system includes an enlarging optical system that enlarges a section of an incident light, a mask that passes some of a light passing through the enlarging optical system, and a reduction optical system that reduces a section of a light passing through the mask.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 1, 2015
    Assignees: SAMSUNG DISPLAY CO., LTD., LIS CO., LTD.
    Inventors: Jung-Min Lee, Young-Kwan Kim
  • Patent number: 9196704
    Abstract: Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 24, 2015
    Assignee: Intel Corporation
    Inventors: Jacob Jensen, Tahir Ghani, Mark Y. Liu, Harold Kennel, Robert James
  • Patent number: 9147735
    Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: September 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Farrar, Jerome M. Eldridge
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Publication number: 20150041966
    Abstract: Systems and methods are provided for activating dopants in a semiconductor structure. For example, a semiconductor structure including a plurality of dopants is provided. One or more microwave-absorption materials are provided, the microwave-absorption materials being capable of increasing an electric field density associated with the semiconductor structure. Microwave radiation is applied to the microwave-absorption materials and the semiconductor structure to activate the plurality of dopants for fabricating semiconductor devices. The microwave-absorption materials are configured to increase the electric field density in response to the microwave radiation so as to increase the semiconductor structure's absorption of the microwave radiation to activate the dopants.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Cheng-Yan Zhan, Yi-Tang Lin, Clement Hsingjen Wann
  • Patent number: 8951895
    Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin Andrew Brenner, Raghunath Murali
  • Patent number: 8946062
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Martin D. Bracamonte
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8815754
    Abstract: New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: August 26, 2014
    Assignee: Rohm and Haas Electronics Materials LLC
    Inventor: Gerhard Pohlers
  • Patent number: 8802549
    Abstract: Methods, systems, and devices associated with surface modifying a semiconductor material are taught. One such method includes providing a semiconductor material having a target region and providing a dopant fluid layer that is adjacent to the target region of the semiconductor material, where the dopant fluid layer includes at least one dopant. The target region of the semiconductor material is lased so as to incorporate the dopant or to surface modify the semiconductor material. During the surface modification, the dopant in the dopant fluid layer is actively replenished.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 12, 2014
    Assignee: SiOnyx, Inc.
    Inventors: Jason Sickler, Keith Donaldson
  • Patent number: 8791387
    Abstract: To provide a laser cutting method that is capable of cutting the substrates high accurately with high throughput at a low cost. It is a laser cutting method for cutting a laminated substrate that is formed by laminating at least a pair of substrates. The method comprises the steps of: providing a pattern member with a characteristic of absorbing light of a wavelength that transmits each of the substrates, between each of the substrates along a cutting position of the laminated substrate; and irradiating a laser of the wavelength that transmits the substrates along the pattern member, whereby the laminated substrate is cut along the pattern member.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: July 29, 2014
    Assignee: NLT Technologies, Ltd.
    Inventors: Tsutomu Hiroya, Kouji Shigemura
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Publication number: 20140159120
    Abstract: Methods for doping a three-dimensional semiconductor structure are disclosed. A conformal coating is formed on the three-dimensional semiconductor structure by Atomic Layer Deposition, and subsequent annealing causes dopant atoms to migrate into the three-dimensional semiconductor structure. Any residual conformal coating is then removed by etching. The semiconductor can be a type IV semiconductor such as Si, SiC, SiGe, or Ge, for which Sb and Te are suitable dopants. Sb and Te can be provided from a Ge2Sb2Te5 conformal coating. The semiconductor can also be a type III-V semiconductor such as InGaAs, GaAs, InAs, or GaSb, for which Sn and S are suitable dopants. Sn and S can be provided from a SnS conformal coating. The dopant concentration can be adjusted by precise control over the number of monolayers deposited in a conformal coating layer deposited by ALD.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventor: Khaled Ahmed
  • Patent number: 8748236
    Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 10, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Atsushi Tanida
  • Patent number: 8741750
    Abstract: A method for fabricating a semiconductor body is presented. The semiconductor body includes a p-conducting zone, an n-conducting zone and a pn junction in a depth T1 in the semiconductor body between the p-conducting zone and the n-conducting zone. The method includes providing the semiconductor body, producing the p-doped zone by the diffusion of an impurity that forms an acceptor in a first direction into the semiconductor body, and producing the n-conducting zone by the implantation of protons in the first direction into the semiconductor body into a depth T2>T1 and the subsequent heat treatment of the semiconductor body in order to form hydrogen-induced donors.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Hille, Franz Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
  • Patent number: 8728921
    Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim Corbett
  • Patent number: 8703582
    Abstract: An element-group formation substrate (20) having plural semiconductor light emitting elements (21) formed on a substrate front surface (11a) is sequentially irradiated with a laser beam (64) having a first output from a substrate back surface (11b) side in the y direction, and the laser beam (64) is sequentially collected to a part having a first depth D1 from the substrate back surface (11b), thereby forming a first modified region L1. The substrate (20) having the first modified region L1 formed therein is sequentially irradiated with the laser beam (64) having a third output (<the first output) from the substrate back surface 11b side in the y direction, and the laser beam (64) is sequentially collected to a part having a third depth D3 from the substrate back surface (11b) shallower than the first depth D1, thereby forming a third modified region L3.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 22, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yoshinori Abe
  • Publication number: 20140106551
    Abstract: Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam. Deep contacts have been found to be effective for producing efficient solar cells. Dielectric layers can be effectively patterned to provide for selected contact between the current collectors and the doped domains along the semiconductor surface. Rapid processing approaches are suitable for efficient production processes.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Applicant: NanoGram Corporation
    Inventors: Uma Srinivasan, Xin Zhou, Henry Hieslmair, Neeraj Pakala
  • Patent number: 8697558
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: April 15, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
  • Patent number: 8673755
    Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device, a second semiconductor device, and a first insulating layer covering the first semiconductor device and the second semiconductor device formed thereon, performing an etching process to remove a portion of the first insulating layer to expose a portion of the first semiconductor device and the second semiconductor device, forming a second insulating layer covering the first semiconductor device and the second semiconductor device, performing a first planarization process to remove a portion of the second insulating layer, forming a first gate trench and a second gate trench respectively in the first semiconductor device and the second semiconductor device, and forming a first metal gate and a second metal gate respectively in the first gate trench and the second gate trench.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Chun Chang, Kuang-Hung Huang, Chun-Mao Chiou, Yi-Chung Sheng
  • Patent number: 8669155
    Abstract: A hybrid channel semiconductor device and a method for forming the same are provided.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 11, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8652893
    Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: February 18, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qiuxia Xu, Dapeng Chen
  • Patent number: 8623694
    Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material, resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Rita J. Klein
  • Patent number: 8604584
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 10, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroki Wakimoto, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Patent number: 8603902
    Abstract: Methods and apparatus for processing a substrate (e.g., a semiconductor substrate) is disclosed that includes irradiating at least a portion of the substrate surface with a plurality of short radiation pulses while the surface portion is exposed to a dopant compound. The pulses are selected to have a fluence at the substrate surface that is greater than a melting fluence threshold (a minimum fluence needed for the radiation pulse to cause substrate melting) and less than an ablation fluence threshold (a minimum fluence needed for the radiation pulse to cause substrate ablation). In this manner a quantity of the dopant can be incorporated into the substrate while ensuring that the roughness of the substrate's surface is significantly less than the wavelength of the applied radiation pulses.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: December 10, 2013
    Assignee: President and Fellows of Harvard College
    Inventors: Eric Mazur, Mark Winkler
  • Patent number: 8598050
    Abstract: Disclosed are a laser annealing method and apparatus capable of forming a crystalline semiconductor thin film on the entire surface of a substrate without sacrificing the uniformity of crystallinity in a seam portion in a long-axis direction of laser light, the crystalline semiconductor thin film having good properties and high uniformity to an extent that the seam portion is not visually recognizable. During the irradiation of a linear beam, portions corresponding to the edges of the linear beam are shielded by a mask 10 which is disposed on the optical path of a laser light 2, and the mask 10 is operated so that the amount of shielding is periodically increased and decreased.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: December 3, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8586460
    Abstract: Methods of enabling the use of high wavelength lasers to create shallow melt junctions are disclosed. In some embodiments, the substrate may be preamorphized to change its absorption characteristics prior to the implantation of a dopant. In other embodiments, a single implant may serve to amorphize the substrate and provide dopant. Once the substrate is sufficiently amorphized, a laser melt anneal may be performed. Due to the changes in the absorption characteristics of the substrate, longer wavelength lasers may be used for the anneal, thereby reducing cost.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 19, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Deepak Ramappa
  • Patent number: 8580646
    Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack A. Mandelman, William R. Tonti
  • Patent number: 8530979
    Abstract: Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujikura Ltd.
    Inventors: Shingo Ogura, Yuki Suto
  • Publication number: 20130228902
    Abstract: Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device (500a) of the present invention comprises the steps (a)-(c) described below and is characterized in that the crystal orientation of a first dopant implanted layer (52) is the same as the crystal orientation of a semiconductor layer or a base (10) that is formed of a semiconductor element. (a) A dispersion which contains doped particles is applied to a specific part of a layer or a base. (b) An unsintered dopant implanted layer is obtained by drying the applied dispersion. (c) The specific part of the layer or the base is doped with a p-type or n-type dopant by irradiating the unsintered dopant implanted layer with light, and the unsintered dopant implanted layer is sintered, thereby obtaining a dopant implanted layer that is integrated with the layer or the base.
    Type: Application
    Filed: December 9, 2011
    Publication date: September 5, 2013
    Applicant: TEIJIN LIMITED
    Inventors: Yuka Tomizawa, Yoshinori Ikeda, Tetsuya Imamura
  • Patent number: 8481393
    Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaki Koyama, Fumito Isaka, Akihisa Shimomura, Junpei Momo
  • Patent number: 8435872
    Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama
  • Patent number: 8372762
    Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique and a manufacturing apparatus of a semiconductor device which simplify a lithography step using a photoresist is provided, so that the manufacturing cost is reduced, and the throughput is improved. An irradiated object, in which a light absorbing layer and an insulating layer are stacked over a substrate, is irradiated with a multi-mode laser beam and a single-mode laser beam so that both the laser beams overlap with each other, and an opening is formed by ablation in part of the irradiated object the irradiation of which is performed so that both the laser beams overlap with each other.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirotada Oishi, Koichiro Tanaka
  • Patent number: 8309444
    Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keung Hui, Chun-Lin Chang, Jong-I Mou
  • Patent number: 8288292
    Abstract: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower than silicon nitride.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 16, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: George Andrew Antonelli, Mandyam Sriram, Vishwanathan Rangarajan, Pramod Subramonium
  • Patent number: 8278739
    Abstract: A method for manufacturing is: forming an insulating film over a substrate; forming an amorphous semiconductor film over the insulating film; forming over the amorphous semiconductor film, a silicon nitride film in which a film thickness is equal to or more than 200 nm and equal to or less than 1000 nm, equal to or less than 10 atomic % of oxygen is included, and a relative proportion of nitrogen to silicon is equal to or more than 1.3 and equal to or less than 1.5; irradiating the amorphous semiconductor film with a continuous-wave laser light or a laser light with repetition rate of equal to or more than the wave length of 10 MHz transmitting the silicon nitride film to melt and later crystallize the amorphous semiconductor film to form a crystalline semiconductor film.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Publication number: 20120178203
    Abstract: Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 12, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Virendra V. Rana, Pranav Anbalagan
  • Publication number: 20120145229
    Abstract: A method for irradiating a plate (104) using multiple co-located radiation sources (108-1,108-2,108-3,108-4) includes that each of the multiple co-located radiation sources (108-1,108-2,108-3,108-4) is responsible for irradiating one of a plurality of bounded sub-regions (110-1,110-2,110-3,110-4) in the plate (104). As a result, sub-regions of the plate (104) that are to be irradiated receive relatively even, relatively well-defined radiation from the multiple co-located radiation sources (108-1,108-2,108-3,108-4). An apparatus performs the method, and a solar cell is produced using the method. The method and the apparatus can be applied in laser doping and laser cutting.
    Type: Application
    Filed: March 17, 2009
    Publication date: June 14, 2012
    Applicant: Wuxisuntech Power Co., Ltd.
    Inventors: Jingjia Ji, Fan Zhu, Zhengrong Shi
  • Patent number: 8173473
    Abstract: An apparatus and method for processing the solar cell substrates is provided. In one embodiment, a laser firing chamber for processing solar cell substrates placed in a carrier, comprising a laser module located at a side of the carrier, the laser module being adapted to generate and direct multiple laser beams over an entire surface of a plurality of solar cell substrates, and a transport adapted to convey the carrier through an outputting region of the laser beams.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 8, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Derek Aqui, Steven M. Zuniga, Venkateswaran Subbaraman, Kirk Liebscher, John Alexander, Zhenhua Zhang, Virendra V. S. Rana
  • Patent number: 8148636
    Abstract: A cover (5) includes a first bent portion (5b) and a second bent portion (5c) which are provided in series to be continuous with a lid portion (5a). A casing (2) includes a hole (8) through which the cover is allowed to be inserted/removed and movably inserted into/removed from the casing, and includes a cover locking portion (9) to which the cover is locked in a substantially upright posture while covering an opening portion (4) with the lid portion. The cover can pivot in a fore-and-aft direction at a corner portion (5d) on an inner side of the first bent portion with an inner edge portion (8c) at an intersection between an upper inner wall surface (8a) of the hole and an inner wall surface (3a) of a front wall as a fulcrum. The cover can be displaced between the substantially upright posture and a substantially laid posture.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: April 3, 2012
    Assignee: Nohmi Bosai Ltd.
    Inventor: Kenichi Kato
  • Publication number: 20120068161
    Abstract: A method for forming graphene includes introducing a substrate and a carbon-containing reactant source into a chamber, and radiating a laser beam onto the substrate to decompose the carbon-containing reactant source and form graphene over the substrate using carbon atoms generated by decomposition of the carbon-containing reactant source. A carbon-containing gas (methane) decomposes upon radiation of a laser beam. The carbon-containing gas has a decomposition rate on the order of femtoseconds and the laser beam has a pulse on the order of nanoseconds or more. The graphene is grown in a single layer along the surface of the substrate. Then, the graphene is selectively patterned using a laser beam to form a desired pattern.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 22, 2012
    Inventors: Keon-Jae LEE, In-Sung Choi, Sung-Yool Choi, Byung-Hee Hong
  • Patent number: 8138071
    Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 20, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert Kaim, Joseph D. Sweeney, Oleg Byl, Sharad N. Yedave, Edward E. Jones, Peng Zou, Ying Tang, Barry Lewis Chambers, Richard S. Ray
  • Publication number: 20120051378
    Abstract: Embodiments of the present disclosure provide systems, devices, and methods for photodetection. For example, briefly described, in one embodiment among others, a sensor comprises an array of photodetectors, wherein the reflectance of each of the photodectors is a function of the number of photons incident on the respective photodetector; and an electrical insulator positioned between one of the photodetectors and another one of the photodetectors to reduce diffusion of electrons therebetween.
    Type: Application
    Filed: December 9, 2010
    Publication date: March 1, 2012
    Inventors: Aravinda Kar, Tariq Manzur
  • Patent number: 8114693
    Abstract: A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 14, 2012
    Assignee: Partial Assignment University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar
  • Publication number: 20120032310
    Abstract: A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate (1); formation of a functional layer (2) on a semiconductor surface (11) of the semiconductor substrate (1); and production of at least one doped section (3) on the semiconductor surface (11) by driving a dopant into the semiconductor substrate (1) from the functional layer (2). The functional layer (2) is formed in such a way that it passivates the semiconductor surface (11), acting as a passivation layer upon completion of the semiconductor device.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 9, 2012
    Applicant: Q-CELLS SE
    Inventors: Peter ENGELHART, Stefan BORDIHN, Maximilian SCHERFF, Bernhard KLÖTER
  • Patent number: 8108159
    Abstract: A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Young Yang, Chi-Hwan Lee