Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: A method of manufacturing a semiconductor device having a triple-well structure, includes the steps of: forming a first well layer of a second conductivity type by implanting, as a first ion implantation, impurity ions of the second conductivity type to a specific depth from the surface of a semiconductor substrate of a first conductivity type and then subjecting the semiconductor substrate to an annealing treatment; forming a second ion-implanted region by implanting, as a second ion implantation, impurity ions of the second conductivity type into an end portion of first well layer with a specific width and at a depth from the surface of the semiconductor substrate to the surface of the first well layer to surround the first well layer; forming a third ion-implanted region by implanting, as a third ion implantation, impurity ions of the first conductivity type into a portion of the semiconductor substrate surrounded by the first well layer and the second ion-implanted region and at depth from the surface of

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A fabrication process of a mask ROM is disclosed, which process is effective to suppress the occurrence of punch-through of a memory cell transistor. According to the process, the surface of a P conductivity-type silicon substrate is subjected to thermal oxidation to grow oxides to form a pad oxide film. A silicon nitride film, which acts as an oxidation resisting film, is deposited on the pad oxide film. A resist is formed on the silicon nitride film. The resist has openings where bit lines are to extend. Using the resist as a mask, the silicon nitride film is selectively etched away. Using the resist as a mask, ions of arsenic (As) are introduced by ion implantation to the substrate for formation of N conductivity-type diffusion regions in the subsequent thermal oxidation. These N conductivity-type diffusion regions act as the bit lines. Using the resist as a mask, ions of boron (B) are introduced by ion implantation for formation of P.sup.

Abstract: A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: A method for fabricating a semiconductor device having a buried channel structure, in which impurities having the same conductive type as a well are ion implanted, to increase the ion density beneath the buried channel, thereby enhancing the short channel characteristic and smooth on/off characteristic of MOSFET.

Abstract: A method of manufacturing semiconductor devices yielding devices having impurity regions that are more shallow and exhibit less lateral diffusion than devices manufactured in accordance with prior art techniques. First, arsenic is introduced into a substrate. After the introduction of arsenic, phosphorus is introduced to the same portion of the substrate. The introductions of arsenic and phosphorus may be accomplished using diffusion or ion implantation techniques.

Abstract: In a method for producing a channel region layer in a SiC-layer for providing a voltage-controlled semiconductor device a layer of silicon being one of a) polycrystalline and b) amorphous is applied on top of the SiC-layer, an aperture is etched in the silicon layer extending to the SiC-layer, a surface layer of a certain thickness of the silicon layer is oxidized, and the lateral extension of the channel region layer is determined by removing the oxidized layer and carrying out a further implantation into the area exposed by the so formed enlarged aperture.

Abstract: A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.

Abstract: A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, contacting the solution with a gaseous mixture, which mixture includes hydrogen, water vapor and products of reactions between the hydrogen and the water vapor with the solvent and with silicon dioxide, to form a contacted solution, coating a suitably selected substrate, such as a group III-V compound such as gallium arsenide, with the contacted solution, cooling the coated substrate to precipitate gallium arsenide from the contacted solution onto the substrate, and removing the substrate coated with a layer of gallium arsenide having a p-i-n structure which constitutes the product having an i region dopant concentration of less than about 10.sup.12 cm.sup.-3.