Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.

Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer. A sidewall spacer is formed within the opening. A first trench is etched into the epitaxial layer through the opening. A dopant source layer is formed on the surface of the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant source layer and the spacer are removed. A sacrificial layer is then filled into the first trench. The sacrificial layer and the epitaxial layer within the first region are etched away to form a second trench.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular, methods of manufacturing and devices of a trench type semiconductor devices containing organic refill materials are provided.

Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.

Abstract: A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite to the conductivity type of the semiconductor substrate. Dopant is transported outwardly from the sacrificial plug into the semiconductor substrate surrounding the trench to define a doped region of the second conductivity type in the semiconductor substrate. A first contact is formed that extends through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region. A second contact is formed that extends through the semiconductor and insulator layers to the doped region.

Abstract: An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.

Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer.

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.

Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

Abstract: A doping method for a semiconductor device includes forming a trench in a semiconductor substrate, forming a doped layer doped with a dopant over the undoped layer, and forming a doped region into which the dopant is diffused, wherein the doped region is a portion of the semiconductor substrate in contact with the doped layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region.

Abstract: In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

Abstract: A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract: Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.

Abstract: A semiconductor device has an insulating film and an n-type buried layer. The insulating film is formed in a flat-shaped cavity formed inside a p-type semiconductor substrate and in a trench extending from a surface of the semiconductor substrate to the cavity. The buried layer is formed in surrounding regions of the cavity and the trench in the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall.

Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench.

Abstract: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.