Abstract: Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:(a) applying a dopant-containing oxide glass layer on the semiconductor surface,(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer,(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

Abstract: A method of making a semiconductor device includes a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer. A transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.

Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.

Abstract: A method of making a shallow trench isolation region includes providing a silicon substrate. A pad oxide layer is formed over the silicon substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer and the pad oxide layer are patterned, and a trench is thus formed in the silicon substrate. A side-wall oxide layer is formed on a surface of the silicon substrate within the trench. A doped oxide layer is formed over the silicon nitride layer and within the trench. A portion of the doped oxide layer is removed to expose the silicon nitride layer. The silicon nitride layer is removed. The pad oxide layer is removed. A sacrificial oxide layer is formed over the silicon substrate. A well is formed in the silicon substrate. The sacrificial oxide layer is removed. A gate oxide layer is formed over the silicon substrate. A polysilicon layer is formed over the silicon substrate. The polysilicon layer is patterned to form a polysilicon gate.

Abstract: A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.

Abstract: A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.

Abstract: A method for producing a diffusion region adjacent to a recess in a substrate, with which structured diffusion regions can be produced within a recess is provided. The method is suitable, in particular, for producing diffusion regions of different conductivity type, which are arranged adjacent to one and the same recess or different recesses.

Abstract: A trench capacitor with a buried plate is formed with a single etching process by the expedient of filling the trench so formed and lined with diffusion source material with resist by baking and reflowing the resist which also serves to adjust exposure sensitivity of the resist such that exposure and development of the resist removes the resist to a repeatable and uniform depth. Remaining resist allows etching of the diffusion source layer to a very accurate dimension. Thus only a readily formed oxide or TECS layer is needed to confine impurities during diffusion to form the buried plate. An isolation collar can be formed after recess of the fill to avoid formation of step corners and erosion of the isolation collar by repeated fill and etch back processes while permitting maximum capacitance to be achieved for a given trench "footprint".