Abstract: The invention relates to the manufacture of a so-called double poly bipolar transistor. In a layer structure of a first insulating layer (4), a polycrystalline layer (5) of silicon and a second insulating layer (6), an opening (7) is formed which extends to a monocrystalline part of the semiconductor body (10), a third insulating layer (8) being provided on the bottom of the opening (7). Via the opening (7) at least a part (1A) of the base (1) is formed. By means of a further opening (9) in the third insulating layer (8), the emitter (3) is formed. A drawback of the known method resides in that the transistors obtained by means of said method exhibit a relatively great spread in electrical characteristics, such as a base current which is not ideal and demonstrates a spread.

Abstract: An improved method of fabricating a MOS transistor on a semiconductor wafer is disclosed. A pre-amorphization implant (PAI) process is used to dope the silicon substrate adjacent to the gate. The dopants formed in the silicon substrate during the first ion implantation process are driven into the substrate to form the HDD via a salicide process. A conventional annealing process is skipped in the present invention, which significantly reduces the thermal budget of the manufacturing process.

Abstract: An ion implanting process allows for shallow source and drain junctions of the transistor. According to one example embodiment, a BARC layer is formed over a gate, and a poly-crystalline or amorphous silicon shield is deposited over the source and drain regions, then the BARC and silicon are chemically mechanically polished. The poly-crystalline or amorphous silicon shield absorbs the initial impact the dopant species of ion implantation and reduces the incidence of irreversible source/drain crystal damage caused by the process. After the ion implantation, the species implanted in the poly or amorphous silicon is diffused into the source/drain regions by annealing. An additional siliciding of the poly or amorphous silicon covering the source and drain minimizes the need for deeper source/drain junctions and hence improves short-channel properties.

Abstract: A method for making an improved polysilicon emitter for a bipolar transistor in a BiCMOS integrated circuit is achieved. The method uses a novel stacked undoped amorphous silicon layer and a doped polysilicon layer. The polysilicon layer is doped by ion implantation while the amorphous silicon layer remains undoped. The stacked layer is patterned to form a polysilicon emitter source over the bipolar transistor, while concurrently forming gate electrodes for the FETs. The undoped amorphous silicon layer retards the diffusion from the doped polysilicon to provide a shallower emitter junction during subsequent thermal processing. At a later step a rapid thermal anneal (RTA) is carried out in which the amorphous silicon layer provides better control of the diffused emitter depth (junction) while concurrently activating the implant dopant in the FET source/drain areas.

Abstract: A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed.

Abstract: Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein.

Abstract: In the manufacture of a semiconductor power device such as a trench-gate power MOSFET, a source region (13) is formed using a sidewall extension (30) of an upstanding insulated-gate structure (11,21,22). The sidewall extension (30) forms a step with an adjacent surface area (10a′) of a body region (15) of a first conductivity type and comprises doped semiconductor material (13a) of opposite, second conductivity type which is separated from the gate (11) by insulating material (22). The body region (15) provides a channel-accommodating portion (15a) adjacent to the gate structure (11,21,22) and also comprises a localised high-doped portion (15b) which extends to a greater depth in the semiconductor body (10) than the shallow p-n junction between the source region (13) and the channel-accommodating portion (15a), and preferably deeper even than the bottom of the trench (20) of a trench-gate device.

Abstract: A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Abstract: A method for forming a flash memory cell forms an insulating layer on a provided substrate and a number of openings are formed within the insulating layer to expose the substrate. A patterned conductive layer having a dopant is formed and fills the openings on the substrate. By driving the dopant into the substrate, source/drain regions are formed. A gate structure is formed on a channel region between the source/drain regions to accomplish the flash memory cell.

Abstract: The upper surface of a field oxide film 102 is made planar to eliminate a swell normally formed. More specifically, the field oxide film 102 is formed by recess LOCOS method so as to be convex formed in the direction toward the inside of a substrate 101 while having an upper surface that is substantially planar.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: Methods of forming field effect transistors include the steps of forming an insulated gate electrode on a face of a substrate containing a semiconductor region therein extending to the face. A conductive layer of first conductivity type is also formed on the face and on a sidewall and upper surface of the insulated gate electrode. Dopants of first conductivity type are then diffused from the conductive layer into the semiconductor region to define source and drain regions of first conductivity type therein which are self-aligned to the insulated gate electrode. A step is also performed to remove a portion of the conductive layer to thereby define an intermediate source/drain contact (which is also self-aligned to the insulated gate electrode) and expose the upper surface of the insulated gate electrode. An electrode is then formed in contact with the intermediate source/drain contact.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

Abstract: A method of manufacturing an electron tunnel oxide (ETOX) flash memory device having an improved coupling efficiency includes sequentially forming a tunnel oxide, a floating gate, a dielectric layer, and a control gate on a substrate, where the tunnel oxide and the bottom of the floating gate are formed to be narrower than the top of the floating gate, the dielectric and the control gate.

Abstract: A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a gate electrode structure; depositing a first dielectric layer and a second dielectric layer; removing the top portion of the second dielectric layer to expose the portion of the first dielectric layer that covers the gate electrode structure; forming on the substrate a patterned resist layer to mask portions of the second dielectric layer; forming trenches next to the gate electrode structure by removing the unmasked portions of the second dielectric layer; filling the trenches with a conductor; doping the conductor with dopants; and driving the dopants into the substrate to form the raised source and drain.

Abstract: The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract: A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Abstract: A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode.

Abstract: A method of forming a transistor is disclosed that comprises the step forming a gate insulator layer 12 on an outer surface of the substrate 10. A first gate conductor layer 22 is formed outwardly from the gate insulator layer 12. The first gate conductor layer 22 is extremely thin. Dopants are introduced into the layer 22 to render it conductive by using a diffusion source layer 24. The diffusion source layer 24 is then removed and replaced by a second gate conductor layer 26 having low resistance. The layer 26 can be used to form a T-gate structure 28, a flush gate 30, or a conventional gate structure.

Abstract: A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

Abstract: A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief layer to expose a desired buried contact area of the substrate; c) masking over the stress relief layer and over the desired buried contact area; d) with the masking in place, exposing the substrate to oxidation conditions effective to grow field oxide regions in unmasked areas of the substrate; e) after forming the field oxide regions, removing the masking from the substrate and effectively leaving the buried contact area exposed; f) providing a layer of electrically conductive material over field oxide and exposed buried contact area; and g) patterning the conductive material layer into a conductive line which overlies both field oxide and the buried contact area.

Abstract: A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.

Abstract: The semiconductor memory device comprises a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another; a plurality of memory cells disposed in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor; a plurality of bit lines extending in a row direction; a plurality of word lines extending in a column direction; a plurality of memory cell pairs, each formed in one of the element regions and including adjacent two of the memory cells disposed in the row direction, wherein each of the transistors of the two memory cells in each memory cell pair has two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film; a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each transistor so as

Abstract: A semiconductor processing method of forming a field effect transistor gate over a semiconductor substrate includes forming a gate dielectric layer over substrate active area while a buried contact mask to said active area is in place. A field effect transistor gate is formed over the gate dielectric layer. A semiconductor processing method of forming a conductive line over a substrate active area includes forming a buried contact mask within a substrate active area from only a portion of a prior used field oxide mask. With the buried contact mask in place, a conductive line is formed that overlies the substrate active area. A semiconductor processing method of forming an electrical connection to a buried contact area of a substrate includes forming a buried contact mask in a substrate active area from a prior used field oxide mask. With the buried contact mask in place, a first conductive line is formed over at least some of the active area adjacent the buried contact mask.

Abstract: A method of making a semiconductor device includes a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer. A transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.

Abstract: A method of making a semiconductor device forms a gate on a substrate and provides a self-aligned diffusion source on the substrate, without the use of a mask. The diffusion source provides dopant material into the substrate. The self-aligning of the diffusion source avoids misalignment of the mask and improper doping. When the diffusion source is polysilicon or amorphous silicon, subsequent patterning and siliciding of the polysilicon forms silicided interconnect straps available for interconnecting devices on the semiconductor wafer.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: A method of manufacturing a raised source/drain semiconductor device is disclosed. When the shallow junction technique is applied, over etching of the source/drain regions during contact etching and salicide processing will lead to current leakage. The invention provides a method which comprises depositing a buffer conductive layer above the substrate and removing a portion of this layer to form buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions.

Abstract: A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process.

Abstract: An improved bipolar transistor of BiCMOS is provided to improve the breakdown voltage between a collector and a base. A low concentration diffusion layer is provided at a main surface of a semiconductor substrate at a boundary between an outer perimeter of an external base layer and an end portion of a field oxide film. The low concentration diffusion layer expands from the main surface of the semiconductor substrate toward the inside of the substrate and has a concentration lower than the impurity concentration of the external base layer.

Abstract: After forming an isolation layer and a well region on and in a silicon substrate, a gate oxide layer, a gate electrode of polycrystalline silicon and an oxide layer on the gate electrode are formed. Subsequently, a side wall of a nitride layer is formed. Then, the oxide layer on the gate electrode is removed. Next, selective growth of impurity doped silicon is performed at a temperature lower than or equal to 800.degree. C. to form an elevated source-drain region in a source-drain region. Also, a polycrystalline silicon layer is formed on the gate electrode. Thereafter, by performing heat treatment, the impurity is diffused from the source-drain region to the surface of the silicon substrate to form a source-drain diffusion layer. Simultaneously, conductivity is provided to the entire gate electrode by diffusing impurity from the polycrystalline silicon layer to the gate electrode.

Abstract: An oxide film is deposited on a semiconductor substrate on which a field oxide film and a gate electrode are formed. The oxide film is etched back to form a first sidewall insulating film made of the oxide film on a side surface of the gate electrode. Then a silicon film is selectively grown on the gate electrode and on the semiconductor substrate. Thereafter a thermal oxide film is formed on a surface of the silicon film by thermally oxidizing. In the step of thermal oxidation, a thin silicon film deposited on a part of the first sidewall insulating film and a part of the field oxide film is fully oxidized. Thereafter, the thermal oxide film is etched back and thereby a second sidewall insulating film made of the thermal oxide film is formed on a side surface of the silicon film.

Abstract: A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as an anti-reflective coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the oxide layer are patterned to form ultra short channel polysilicon gates. A thermal annealing is performed to recover the etching damage in the substrate and generate a pad oxide layer on the surface of the polysilicon gate and the substrate. An nitrogen-doped amorphous silicon layer is formed on the gate structure and on the pad oxide. Next, an ion implantation is carried out to dope dopants into the gate and substrate, thereby forming source and drain. A steam oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon dioxide layer.

Abstract: A method (10) of phosphorus doping a semiconductor particle using ammonium phosphate. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried (16, 18), with the phosphorus then being diffused (20) into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement.

Abstract: A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the isolation structure, depositing a polysilicon blanket layer overlying the thin oxide layer, patterning a photoresist mask overlying the polysilicon blanket layer and implanting dopant impurities into the polysilicon blanket layer. The method further includes steps of diffusing the dopant impurities from the polysilicon blanket layer through the thin oxide layer into the integrated circuit device channel, removing the polysilicon blanket layer, and removing the thin oxide layer.

Abstract: This invention provides a transistor manufacture method comprising the steps of forming, on a semiconductor substrate, an insulating film being made open at least in an introducing portion through which an impurity for forming a drain region other than a lightly-doped region is introduced, then forming a gate electrode and a drain electrode each containing an impurity, and then introducing the impurity through between the gate electrode and the drain electrode to thereby form the lightly-doped region; and introducing the impurity from the drain electrode through the impurity introducing portion with heat treatment, to thereby form the drain region. A transistor manufactured by the above method is also provided.

Abstract: A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

Abstract: A semiconductor device and process for manufacture thereof is disclosed in which an elevated, active polysilicon region is formed by forming a gate electrode/nitride layer structure on a surface of a semiconductor substrate with spacers formed on adjacent walls to define an active region of the substrate. A thick polysilicon layer is formed over the resultant structure and then planarized leaving a portion of the polysilicon layer above the active region of the substrate. The remaining portion is doped to form an elevated active region.