Abstract: A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.

Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Abstract: A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening.

Abstract: A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.

Abstract: In a method of introducing phosphorous into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the lightly doped drain (LDD) implant step, with the exception, that, in this case, the gate polysilicon remains undoped. In accordance with the invention, dopant is then implanted into the source/drain regions such that the undoped gate polysilicon is amorphized, thereby eliminating the polysilicon grain boundaries. A CVD oxide layer is then formed and a CMP step is performed to expose the amorphized gate polysilicon region. A phosphorous oxychloride (POCl.sub.3) layer is then formed over the amorphized gate polysilicon and thermally annealed to drive phosphorous from the POCl.sub.3 layer into the polysilicon. The POCl.sub.3 layer is then removed.

Abstract: A thin film transistor is fabricated by introducing a dopant into an indium tin oxide layer or a gate insulating layer by an ion shower doping technique. An a-Si semiconductor layer is then deposited on the surface of the substrate and subjected to a single exposure of laser light. The laser exposure or annealing diffuses dopant into the semiconductor layer and activates the dopant to form an ohmic layer of n-type or p-type conductivity polysilicon, and an intrinsic polysilicon layer. A metal layer and an indium tin oxide layer are formed to the side of a gate electrode to maintain an electrical connection even if a break is formed in the data bus line.

Abstract: A new method for manufacturing an MOS transistor is applied in the deep submicron process. In this method, a polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process. This method can reduce short channel effects and the series impedance of the source/drain as well as accomplish the local interconnection of a circuit and planarization. Therefore, this method is very suitable for manufacturing devices in the deep submicron process.

Abstract: A method of manufacturing semiconductor devices yielding devices having impurity regions that are more shallow and exhibit less lateral diffusion than devices manufactured in accordance with prior art techniques. First, arsenic is introduced into a substrate. After the introduction of arsenic, phosphorus is introduced to the same portion of the substrate. The introductions of arsenic and phosphorus may be accomplished using diffusion or ion implantation techniques.

Abstract: A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: A method for forming al buried contact begins by forming an exposed contact area (22) of a substrate (10) having a surface (11). An undoped or lightly doped layer of polysilicon (32) is formed in contact with the contact area (22). A contiguous masking layer (36) is formed over one or more of the contact areas (22) to cover a contact portion of the layer (32) while exposing other portions of the layer (32). The other portions of the layer (32) are doped with dopant atoms (44). A heat cycle is used to laterally drive the dopant atoms (44) through the layer (32) and downward through a substrate surface (11) to form buried contact substrate-diffused regions (54). The resulting regions (54) have improved voltage punch-through resistance to laterally adjacent electrical diffusion regions since the masking layer (36) creates a longer thermal diffusion path for the dopant atoms which eventually reside in the regions (54).

Abstract: A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to insulate the gate electrode; forming a gate insulating film; forming an amorphous polysilicon film over the resulting structure; and forming a source/drain region by diffusing the dopants of the doped polysilicon film into the amorphous silicon film, whereby it is possible to form the source/drain region and drain offset structure of a thin film transistor without formation of a source/drain mask and ion implantation and thus, thereby simplifying the overall procedure.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: An ultrahigh speed bipolar transistor has a base region which is formed from a P.sup.+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.

Abstract: Methods of forming field effect transistors.

Abstract: A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

Abstract: A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief layer to expose a desired buried contact area of the substrate; c) masking over the stress relief layer and over the desired buried contact area; d) with the masking in place, exposing the substrate to oxidation conditions effective to grow field oxide regions in unmasked areas of the substrate; e) after forming the field oxide regions, removing the masking from the substrate and effectively leaving the buried contact area exposed; f) providing a layer of electrically conductive material over field oxide and exposed buried contact area; and g) patterning the conductive material layer into a conductive line which overlies both field oxide and the buried contact area.

Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Abstract: An improved reverse self-aligned FET having subquarter-micrometer channel lengths, shallow junction depths, and silicide source/drain contacts was achieved. The method for fabricating the FET includes forming a titanium layer, an N.sup.+ doped first polysilicon layer, and a silicon nitride layer over the device areas. A photoresist mask having first openings with minimal feature size is formed over the device areas where gate electrodes are desired. Non-volatile polymer sidewall spacers are formed on the side-walls of the first openings to extend the resolution limit of the photoresist. The sidewalls and photoresist are used as a mask to etch the silicon nitride layer, the first polysilicon layer, and the titanium layer to the substrate to form second openings (FET channel openings) where the gate electrodes are to be formed. A gate oxide is grown on the substrate in the channel openings, and a threshold-voltage implant and an anti-punchthrough implant are carried out in the channel openings, and then an N.

Abstract: A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.

Abstract: A method for forming memory cells, featuring a bit line, embedded in an insulator filled, shallow trench, has been developed. Self-alignment of the buried bit line, to a source and drain region of a transfer gate transistor, is obtained via outdiffusion of a doped polysilicon layer, used as part of the buried bit line, composite layer.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.